The First Compact Model to Determine $V_{T}$ Distribution for DG-FinFET Due to LER
TL;DR: The first compact model to estimate the distribution of double gate-FinFET due to line edge roughness shows a good match with well-calibrated TCAD data and demonstrates an excellent accuracy for a wide range of scaling and variability parameters.
Abstract: We report the first compact model to estimate the ${V}_{T}$ distribution of double gate-FinFET due to line edge roughness. We derive closed-form expressions, representing the compact model, for: 1) mean and standard deviation of fin width ( ${W}_{\text {fin}}$ ) in terms of geometrical and variability parameters of the FinFET; 2) ${V}_{T}$ as a function of ${W}_{\mathrm {fin}}$ for uniform width fins; and 3) ${V}_{T}$ in tapered fins using percolation. The ${V}_{T}$ distribution produced from the compact model shows a good match with well-calibrated TCAD data and demonstrates an excellent accuracy (~3mV rms error) for a wide range of scaling and variability parameters. The model is simple, platform independent, and $\sim {\text {10}}^{\text {4}}{\times }$ faster compared to TCAD. It enables intuitive understanding of design space for FinFET on the one hand, and accurate FinFET variability-aware circuits and system design on the other hand.
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TL;DR: A ML (Machine Learning)-based artificial neural network (ANN) model is proposed to estimate the LER (line edge roughness)-induced performance variation in Fin-shaped Field Effect Transistor (FinFET).
Abstract: ML (Machine Learning)-based artificial neural network (ANN) model is proposed to estimate the LER (line edge roughness)-induced performance variation in Fin-shaped Field Effect Transistor (FinFET). For a given LER features such as rms amplitude(Δ), correlation length along x-direction (A
X
), and correlation length along y-direction (A
Y
), the metrics for device performance such as on-state drive current, off-state leakage current, threshold voltage, and subthreshold swing can be computing-efficiently estimated with the ANN model.
12 citations
Cites background or result from "The First Compact Model to Determin..."
...Nevertheless, due to many technical barriers in developing a new compact model, the compact model for analyzing the impact of LER [14], [15] would not be timely developed, even though the LER on the fin sidewall of FinFET should bemodeled for two-dimensionally characterizing/understanding the sidewall surface [7], [13]....
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...In real, α is usually out of sight in many other studies on LER [11], [14], [15], [20]....
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...Thus, a few studies [14], [15] have tried to compactly model the impact of LER on the device performance....
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TL;DR: In this article, the impact of metal gate granularity (MGG) and line edge roughness (LER) on the threshold voltage (V T ) of FinFETs has been investigated.
Abstract: Process-induced variation (PIV) is the major bottleneck for using advanced CMOS technology efficiently. Even though the multigate nature of the fin field effect transistor (FinFET), nano-wire FET (NWFET), and nanosheet FET (NSFET) make the device robust toward the short channel effects (SCEs), unpredictable device-to-device variation caused by unwanted PIV remains a challenge for the designers. In this article, we propose a generic variability model to describe the impact of PIV on performance parameters of advanced devices. The major focus of this article is to demonstrate two independent analytical models capturing the impact of metal gate granularity (MGG) and line edge roughness (LER) on the threshold voltage ( V T ) of FinFET. The proposed model is not only limited to the variability estimation of V T , but also capable of estimating the on-current ( I on), subthreshold slope (SS), and off-current ( I off) distribution due to LER accurately. Both the models are generic enough to be extended to be used for NWFET, and NSFET, and utilizes simple physics and mathematics, therefore, it can be implemented in any platform. The models are 100-1,000 times faster in comparison to the technology CAD (TCAD) simulations, and accuracy is on par with the TCAD results. Such models, when integrated with the existing nominal SPICE setup, the circuit-level performance prediction will be comparable to the experimental results. As the models take process-generated variations as an input to produce corresponding performance variation, it will further enable the co-optimization of the process as well as the circuit performance.
9 citations
Cites methods from "The First Compact Model to Determin..."
...DECEMBER 2020 | IEEE NANOTECHNOLOGY MAGAZINE | 13 The , a , b and c parameters in (9) are calibrated using TCAD data [Figure 9(c)] [27]....
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...K The correlation between two opposite f in edges—say x L1^ h and , x L 2^ h where [ ] x dxN 0 ! and N is the number of elements in the x array [27]—is implemented using the Cholesky decomposition expression mentioned in (4) [28], and quantif ied using the correlation coefficient ( )....
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...A detailed description of the LER-infused FinFET structure creation in SDE TCAD is reported in our previous work [27], [30], [33]....
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...With this information, we derive an expression for W x avg T ^ h presented in (8), where / C N dx = is a scaling constant defined in our previous work [27], and the standard deviation of , x Wavg T ^ h i....
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...Further validation of the model is reported in detail in our previous work [27], [30]....
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TL;DR: In this article , an accurate process-induced variability (PIV) aware compact model-based circuit performance estimation for design-technology co-optimization (DTCO) was carried out using an experimentally validated BSIM-CMG model.
Abstract: In sub-10nm FinFETs, Line-edge-roughness (LER) and metal-gate granularity (MGG) are the two most dominant sources of variability and are mostly modeled semi-empirically. In this work, compact models of LER and MGG are used. We show an accurate process-induced variability (PIV) aware compact model-based circuit performance estimation for Design-Technology Co-optimization (DTCO). This work is carried out using an experimentally validated BSIM-CMG model on a 7nm FinFET node. First, we have shown performance bench-marking of LER and MGG models with the state-of-the-art and shown {\textbackslash}4x({\textbackslash}2.3x) accuracy improvement for NMOS(PMOS) in the estimation of device figure of merits (DFoMs). Second, RO and SRAM circuits performance estimation is carried out for LER and MGG variability. Further, {\textbackslash}22\% more optimistic estimate of ({\sigma}/{\mu})\textsubscript{SHM} (Static Hold Margin) compared to the state-of-the-art model with V\textsubscript{DD} variation is shown. Finally, we demonstrate our improved DFoMs accuracy translated to more accurate circuits figure of merits (CFoMs) performance estimation. For worst-case SHM (3({\sigma}/{\mu})\textsubscript{SHM}@VDD=0.75 V) compared to state-of-the-art, dynamic(standby) power reduction by {\textbackslash}73\%({\textbackslash}61\%) is shown. Thus, our enhanced variability model accuracy enables more credible DTCO with significantly better performance estimates.
1 citations
TL;DR: In this paper , a generative adversarial network (GAN) is proposed to estimate the LER-induced random variations of the transistor's electrical characteristics during fabrication of Fin-shaped Field Effect Transistor (FET).
Abstract: For higher density of transistors in Integrated Circuit (IC), various scaling technologies have been introduced. In the light of the physical limit in advancing single-gate transistor architecture, the structural transition from planar device architecture toward 3D device architecture (of which the representative one is Fin-shaped Field-Effect Transistor, or FinFET) manifests itself. However, during fabrication, the unexpected process-induced random variations of the transistor’s electrical characteristics have become more extreme with aggressively scaling down the physical dimension of transistor as well as with evolving from 2D to 3D device structure. Consequently, accurate and rapid estimation of the random variations conditioned on the variation sources (e.g., LER, RDF, and WFV) is required. Recently, machine learning-based approaches were utilized to estimate the LER-induced variations, but they were highly dependent on modeling and evaluation assumptions (e.g., Gaussian or independence). To that end, firstly, we introduce a GAN-based framework for the estimation of process-induced random variations. Since GAN is free from distributional assumptions, this enables precise prediction and, more importantly, enables unified estimation, i.e., adaptable to various variation sources. Secondly, to achieve better generalization on unseen conditions, we additionally suggest a two-step learning strategy utilizing the latest Conditional GAN models. Thirdly, we introduce sample-based evaluation procedure which measures the difference between two sample sets from a probabilistic perspective. Finally, the evaluation results on LER and RDF/WFV datasets show that our GAN-based framework is computationally efficient and is able to generate synthetic samples similar to the TCAD simulated samples that contain random variations, both qualitatively and quantitatively. From such results, our GAN-based framework is expected to be successfully applied to real data, and consequently be able to reliably estimate the random variations of fabricated transistors with multiple orders of magnitude speed-up compared to the conventional TCAD simulation-based estimation.
TL;DR: In this article , a semi-analytical compact model of random process fluctuations in nanosheet (NS) gate-all-around (GAA) complementary FET (CFET) is proposed, including work-function variation (WFV), line edge roughness (LER), and gate edge roughs (GER).
Abstract: In this work, a semi-analytical compact model of random process fluctuations in nanosheet (NS) gate-all-around (GAA) complementary FET (CFET) is proposed, including work-function variation (WFV), line edge roughness (LER), and gate edge roughness (GER). Different from the conventional NS GAA FET, GER has a significantly different impact on NS GAA CFET, due to the additional p-type work-function (p-WF) liner for p-FET threshold voltage tuning as well as the common metal gate, and a negative correlation with p-WF thickness is introduced into GER model. The proposed model is embedded into Berkeley short-channel insulated-gate field-effect transistor model-common multi-gate (BSIM-CMG) to predict the device performance variability by HSPICE Monte Carlo (MC) simulations. Excellent agreement between stochastic TCAD and HSPICE MC simulations is demonstrated. The effect of process variations on the power-performance-area (PPA) of standard cells (SDCs) and ring oscillator (RO) circuit is predicted by the proposed model. Most of the process variations make a more than $-$ 10% to $+$ 20% change in power consumption in NOR2. WFV has the greatest impact on RO PPA, making a $-$ 10% to $+$ 12.3% change in power consumption. The proposed model provides a helpful guideline for the random variation-aware CFET circuit design and related technology process development.
References
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Book•
17 Oct 2007
TL;DR: FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FET) and explains the physics and properties.
Abstract: FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.
843 citations
"The First Compact Model to Determin..." refers methods in this paper
...INTRODUCTION F inFET has enabled sub-20-nm technology node for the CMOS process by enhancing the gate control in comparison to planar and double-gate MOSFETs [1]....
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...[3] A. Asenov, S. Kaya, and A. R. Brown, “Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness,” IEEE Trans....
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...I. INTRODUCTION F inFET has enabled sub-20-nm technology node for theCMOS process by enhancing the gate control in comparison to planar and double-gate MOSFETs [1]....
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TL;DR: In this paper, the impact of the gate line edge roughness (LER) on the intrinsic parameters fluctuations in deep decananometer (sub 50 nm) gate MOSFETs was investigated.
Abstract: In this paper, we use statistical three-dimensional (3-D) simulations to study the impact of the gate line edge roughness (LER) on the intrinsic parameters fluctuations in deep decananometer (sub 50 nm) gate MOSFETs. The line edge roughness is introduced using a Fourier synthesis technique based on the power spectrum of a Gaussian autocorrelation function. In carefully designed simulation experiments, we investigate the impact of the rms amplitude /spl Delta/ and the correlation length /spl Lambda/ on the intrinsic parameter fluctuations in well scaled, but simple devices with fixed geometry as well as the channel length and width dependence of the fluctuations at fixed LER parameters. For the first time, we superimpose in the simulations LER and random discrete dopants and investigate their relative contribution to the intrinsic parameter fluctuations in the investigated devices. For particular MOSFET geometries, we were able to identify the regions where each of these two sources of intrinsic parameter fluctuations dominates.
612 citations
"The First Compact Model to Determin..." refers background or methods in this paper
...Generation of ρ Correlated Random Lines First, for given ρ, , and σLER, we use a Gaussian power spectral density (PSD) [3] function given in (1) to generate random lines l1(x) and l2(x) shown in (2) PSD(k) = C2 √ πσ 2 LER e − k 2 2...
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...Constant C = √N/dx is normalization constant used to fit the experimental LER data presented in [3], where, dx is the discrete Fig....
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...The random lines are generated using Gaussian PSD [3], and ρ correlation is incorporated using the Cholesky decomposition [9]....
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...The parameters defining LER are autocorrelation length ( ) and fin edge variation (σLER) [3]....
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01 Dec 2011
TL;DR: In this paper, a comprehensive 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping is presented.
Abstract: A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping is presented. Excellent electrostatic integrity and resulting tolerance to low channel doping are perceived as the main FinFET advantages, resulting in a dramatic reduction of statistical variability due to random discrete dopants (RDD). It is found that line edge roughness (LER), metal gate granularity (MGG) and interface trapped charges (ITC) dominate the parameter fluctuations with different distribution features, while RDD may result in relatively rare but significant changes in the device characteristics.
268 citations
"The First Compact Model to Determin..." refers background in this paper
...The LER is one of the dominant sources of variability in FinFET, contributing to broadening of the VT distribution [2]....
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...The FER has a dominant effect on VT variability [2], hence going forward; we will consider only FER accounted as LER....
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01 Dec 2015
TL;DR: In this article, the gate edge roughness (GER) and Fin-Edge Roughness (FER) were integrated into the industry standard BSIM-CMG core model for the first time, and the accuracy and predictivity were verified through atomistic TCAD simulations.
Abstract: Predictive compact models for two key variability sources in FinFET technology, the gate edge roughness (GER) and Fin edge roughness (FER), are proposed for the first time, and integrated into industry standard BSIM-CMG core model. Excellent accuracy and predictivity is verified through atomistic TCAD simulations. The inherent correlations between the variations of device electrical parameters are well captured. In addition, an abnormal non-monotonous dependence of variations on Fin-width is observed, which can be explained with the newly found correlation between random variations and electrostatic integrity in FinFETs. The impacts of GER and FER on circuits are efficiently predicted for 16/14nm node and beyond, providing helpful guidelines for variation-aware design and technology process development.
26 citations
"The First Compact Model to Determin..." refers background in this paper
...Effective Wmin (Wmin−eff ) enables both strong and weak QC regimes, based on semiempirically obtained dependence of Wmin−eff on /LG [7]....
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