Proceedings ArticleDOI
The impact of a high-κ gate dielectric on a p-channel tunnel field- effect transistor
Avik Chattopadhyay,Abhijit Mallik +1 more
- Vol. 8549, pp 491-495
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TLDR
In this article, the impact of varying the dielectric constant of the gate dielectrics on the device performance of a double======gate p-channel tunnel field effect transistor (p-TFET) is reported for the first time.Abstract:
In this paper, the impact of varying the dielectric constant of the gate dielectric on the device performance of a double
gate p-channel tunnel field-effect transistor (p-TFET) is reported for the first time. It is observed that fringing field
arising out of a high−κ gate dielectric degrades the device performance of a p-TFET, which is in contrast with its nchannel
counterpart, where the same been reported to yield better performance. Also, the impact of fringing field is
found to be larger for a p-TFET with higher source doping.read more
Citations
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Journal ArticleDOI
Impact of interface traps on direct and alternating current in tunneling field-effect transistors
TL;DR: The results show that the donor-type and acceptor-type ITs have the great influence on DC characteristic at midgap, and the flat band shift changes obviously and differently in the AC analysis, which results in contrast of peak shift of Miller capacitor Cgd for n-type TFETs with donor-like andacceptor-like ITs.
References
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Journal ArticleDOI
Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec
TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Journal ArticleDOI
Performance Enhancement of Vertical Tunnel Field-Effect Transistor with SiGe in the δp+ Layer
TL;DR: In this article, the authors further investigated the performance enhancement with SiGe in the δp+ layer and showed that the subthreshold swing of the vertical tunnel FET is not limited to the theoretical value of 60 mV/dec at room temperature.
Journal ArticleDOI
Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor
TL;DR: In this paper, the effects of varying the dielectric constant and width of the spacer are studied, and it is observed that the use of a low-dielectric as a spacer causes an improvement in its on-state current.
Journal ArticleDOI
Tunnel field effect transistor with increased ON current, low-k spacer and high-k dielectric
TL;DR: In this paper, an improved double-gate tunnel field effect transistor structure with superior performance is proposed, which consists in the introduction of a low-k spacer that is combined with a high-k gate dielectric.
Journal ArticleDOI
Fringing-Induced Drain Current Improvement in the Tunnel Field-Effect Transistor With High- $\kappa$ Gate Dielectrics
TL;DR: In this article, the influence of using a high-kappa gate dielectric in the tunnel FET compared to a standard silicon oxide with same equivalent oxide thickness, which exhibits a quite different behavior compared to conventional MOSFET due to its totally different working principle was evaluated.