Journal ArticleDOI
The power of parallel prefix
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This study assumes the weakest PRAM model, where shared memory locations can only be exclusively read or written (the EREW model) to solve the prefix computation problem, when the order of the elements is specified by a linked list.Abstract:
The prefix computation problem is to compute all n initial products a1* . . . *a1,i=1, . . ., n of a set of n elements, where * is an associative operation. An O(((logn) log(2n/p))XI(n/p)) time deterministic parallel algorithm using p≤n processors is presented to solve the prefix computation problem, when the order of the elements is specified by a linked list. For p≤O(n1-e)(e〉0 any constant), this algorithm achieves linear speedup. Such optimal speedup was previously achieved only by probabilistic algorithms. This study assumes the weakest PRAM model, where shared memory locations can only be exclusively read or written (the EREW model).read more
Citations
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Book ChapterDOI
Massively parallel processing of image contours
TL;DR: The past three decades have seen the emergence of powerful new methods for image analysis and of novel architectural concepts for the design and construction of massively parallel machines, many motivated by the need to process images at high speeds.
AN SIMD PARALLEL &-APPROXIMATION SCHEME FOR On KNAPSACK
TL;DR: A parallel version of a well-known E-approximation scheme for 0/1 knapsack problems is presented and is realizable on currently available, massively parallel computer systems, such as the Connection Machine System.
New parallel prefix algorithms
Yen-Chun Lin,Li-Ling Hung +1 more
TL;DR: Three new families of computation-efficient parallel prefix algorithms for message-passing multicomputers are presented, each providing the flexibility of either fewer computation time steps or fewer communication time steps to achieve the minimal running time.
Journal ArticleDOI
Circuits over monoids: a fault model, and a trade-off between testability and circuit delay
H. A. Farhat,Jean-Camille Birget +1 more
TL;DR: A new fault model for evaluation circuits and prefix circuits over a transformation monoid is introduced and a trade-off between the delay of the circuit and the number of test-inputs needed to detect faultiness is given.