The strictly non-blocking condition for three-stage networks
TL;DR: A criterion for a three-stage network to be strictly non-blocking is presented, which distinguishes between channel grouping and link speedup as methods of increasing the bandwidth available to calls.
Abstract: A criterion for a three-stage network to be strictly non-blocking is presented which is very general in its application. The criterion distinguishes between channel grouping and link speedup as methods of increasing the bandwidth available to calls. It may be applied to both circuit-switched and packet-switched networks. The non-blocking conditions for various networks are shown to be special cases of the condition presented here.
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TL;DR: The analysis presented determines the minimum number of the second-stage switches required for strictly non-blocking operation of generalized three-stage Clos (1953) switching networks in the multirate environment.
Abstract: This paper studies the non-blocking switching operation of generalized three-stage Clos (1953) switching networks in the multirate environment. The analysis presented determines the minimum number of the second-stage switches required for strictly non-blocking operation of such networks at call setup. Both the discrete and the continuous bandwidth cases are considered. For the discrete bandwidth case, sufficient and necessary conditions are derived. For the continuous bandwidth case, only sufficient conditions are given, which, in some cases, also constitute necessary conditions. The results given are, in some cases, generalizations of existing results, but they also include new results.
8 citations
Cites background from "The strictly non-blocking condition..."
...Asymmetrical switch configurations were considered in [ 8 ]....
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Proceedings Article•
01 Feb 2003
TL;DR: A novel design for an asynchronous optical packet switch that has excellent throughput with low latency and low packet loss is presented.
Abstract: We present a novel design for an asynchronous optical packet switch. The architecture is GMPLS-compliant, DWDM-capable and fully scalable. The switch uses a novel in-line buffer design, based on parallel recirculating buffers. The buffers solve contention by statistical multiplexing, and can be configured to conserve packet order and prioritize traffic. The control system is based on a direct local lookup of the destination port and wavelength and traffic class using the packet label. Performance modeling indicates that the switch has excellent throughput with low latency and low packet loss
8 citations
Cites background from "The strictly non-blocking condition..."
...A node of this type is non-blocking [6]....
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01 Jun 1997
TL;DR: This paper studies the nonblocking switching operation of 3–stage Clos networks in the multirate environment and determines bounds for the minimum number of middle-stage switches required for strictly nonblocking operation.
Abstract: This paper studies the nonblocking switching operation of 3–stage Clos networks in the multirate environment. In particular, we concentrate on the strictly nonblocking mode of operation of these switching networks. Our analysis determines bounds for the minimum number of middle-stage switches required for strictly nonblocking operation. Several cases of the multirate environment are considered, including discrete and continuous bandwidth multirate traffic. We survey the results already reported in the literature and we extend them for general asymmetrical Clos networks. We also generalize them for the case in which the internal links have higher bandwidth capabilities than the input/output ports. In addition to these extensions, we derive a more general result, which not only provides a tight bound for various multirate cases, but also improves an already existing bound for the case of continuous bandwidth multirate traffic.
5 citations
Proceedings Article•
01 Jan 2003
TL;DR: This paper directly addresses the performance of the core OPS module and results obtained from simulation models show that the proposed asynchronous OPS architecture exhibits low latency and packet losses allied with relatively high throughput.
Abstract: The prime objective of the EPSRC-funded OPSnet project is the design and demonstration of an asynchronous DWDM optical packet switch (OPS) capable of directly carrying IP packets over DWDM-based core networks at transport rates in the order of 100 Gb/s and above. To achieve such an objective demands a highly flexible and innovative core switch architecture. The operation and performance of such an architecture is the subject of this paper. The paper directly addresses the performance of the core OPS module and results obtained from simulation models show that the proposed asynchronous OPS architecture exhibits low latency and packet losses allied with relatively high throughput
4 citations
Cites background from "The strictly non-blocking condition..."
...The three single-wavelength stages are necessary to ensure the switch is strictly non-blocking [6] and this is a requirement for backward compatibility with circuit switched networks)....
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22 Oct 1998
TL;DR: In this article, conditions under which asymmetrical Clos (1953) networks are strictly non-blocking are determined, and the results obtained provide new necessary and sufficient conditions, and improves already existing bounds for the nonblocking operation of considered networks.
Abstract: Non-blocking three-stage switching networks in the multirate environment are studied. Conditions under which the asymmetrical Clos (1953) networks are strictly non-blocking are determined. The results obtained provides new necessary and sufficient conditions, and improves already existing bounds for the non-blocking operation of considered networks.
2 citations
References
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TL;DR: In this article, the authors describe a method of designing arrays of crosspoints for use in telephone switching systems in which it will always be possible to establish a connection from an idle inlet to an idle outlet regardless of the number of calls served by the system.
Abstract: This paper describes a method of designing arrays of crosspoints for use in telephone switching systems in which it will always be possible to establish a connection from an idle inlet to an idle outlet regardless of the number of calls served by the system.
1,778 citations
TL;DR: A growable switch architecture is presented that is based on three key principles: a generalized knockout principle exploits the statistical behaviour of packet arrivals and thereby reduces the interConnect complexity, output queuing yields the best possible delay/throughput performance, and distributed intelligence in routing packets through the interconnect fabric eliminates internal path conflicts.
Abstract: The problem of designing a large high-performance, broadband packet of ATM (asynchronous transfer mode) switch is discussed. Ways to construct arbitrarily large switches out of modest-size packet switches without sacrificing overall delay/throughput performance are presented. A growable switch architecture is presented that is based on three key principles: a generalized knockout principle exploits the statistical behaviour of packet arrivals and thereby reduces the interconnect complexity, output queuing yields the best possible delay/throughput performance, and distributed intelligence in routing packets through the interconnect fabric eliminates internal path conflicts. Features of the architecture include the guarantee of first-in-first-out packet sequence, broadcast and multicast capabilities, and compatibility with variable-length packets, which avoids the need for packet-size standardization. As a broadband ISDN example, a 2048*2048 configuration with building blocks of 42*16 packet switch modules and 128*128 interconnect modules, both of which fall within existing hardware capabilities, is presented. >
145 citations
27 Nov 1989
TL;DR: A growable switch architecture is proposed based on a generalized knockout principle which exploits the statistical behavior of packet arrivals and thereby reduces the interconnect complexity and output queuing, which yields the best possible delay/throughput performance.
Abstract: The authors consider the generic problem of designing a large N*N(N>1000) high-performance, broadband packet (or asynchronous transfer mode) switch. They provide ways to construct arbitrarily large switches out of modest-size packet switches, without sacrificing overall delay/throughput performance. They propose and study a growable switch architecture based on three key principles: (a) a generalized knockout principle which exploits the statistical behavior of packet arrivals and thereby reduces the interconnect complexity; (b) output queuing, which yields the best possible delay/throughput performance; and (c) distributed intelligence in routing packets through the interconnect fabric. Other features include the guarantee of a first-in first-out packet sequence, broadcast and multicast capabilities, and compatibility with variable-length packets. In a broadband ISDN (integrated services digital network) example, the authors show a 2048*2048 switch configuration with building blocks of 42*16 packet switch modules and 128*128 interconnect modules. >
132 citations
"The strictly non-blocking condition..." refers background in this paper
...Cell-level path allocation has been proposed in the Growable packet switch [10] and in our channel-grouped switch [11]....
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TL;DR: It is found that strictly nonblocking operation can be obtained for multirate traffic with essentially the same complexity as in the classical context.
Abstract: An extension of the classical theory of connection networks is defined and studied. This extension models systems in which multiple connections of differing data rates share the links within a network. Conditions under which the Clos and Cantor networks are strictly nonblocking for multirate traffic are determined. The authors also determine conditions under which the Benes network and variants of the Cantor and Clos networks are rearrangeable. It is found that strictly nonblocking operation can be obtained for multirate traffic with essentially the same complexity as in the classical context.
99 citations
"The strictly non-blocking condition..." refers background or methods or result in this paper
...This result can be shown to be the same as that obtained by Melen and Turner [4]....
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...This result has been obtained by Melen & Turner [4] in the case where S = 1, and is valid for r > 1....
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...5 This result has been obtained by Melen & Turner [4] in the case where S = 1, and is valid for r > 1....
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...A number of authors have sought to extend this result to switches with multiple rates, or multiple channels, and to packet switching [2-9]....
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...It follows that an unstated assumption of Melen and Turner is that the call rate u can occupy a continuum of values in the range from umin to umax....
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TL;DR: In this paper, the performance of a growable architecture for broadband asynchronous transfer mode (ATM) switching consisting of a memoryless self-routing interconnect fabric and modest-size packet switch modules is examined.
Abstract: The performance of a growable architecture for broadband asynchronous transfer mode (ATM) switching consisting of a memoryless self-routing interconnect fabric and modest-size packet switch modules is examined. The cell loss probability is the focus because the architecture attains the best possible delay-throughput performance if the packet switch modules use output queuing. There are two sources of cell loss in the switch. First, cells are dropped if too many simultaneous arrivals are destined to a group of output ports. Second, because a simple, distributed path-assignment controller is used for speed and efficiency, cells are dropped when the controller cannot schedule a path through the switch. The authors compute an upper bound on arrivals, possibly including isochronous circuit connections, and show that both sources of cell loss can be made negligibly small. >
49 citations
"The strictly non-blocking condition..." refers background in this paper
...finite probability of loss can be accepted, for which the required value of m will be considerably reduced [ 12 ,13]....
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