Proceedings ArticleDOI
Thermal characterization of vias using compact models
Damaruganath Pinjala,M.K. Iyer,Chow Seng Guan,I.J. Rasiah +3 more
- pp 144-147
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TLDR
In this paper, the accuracy of compact thermal via models with respect to the detailed models has been determined using PBGA 352 as the test vehicle and found that the accuracy is within 3%.Abstract:
Thermal vias and balls are key elements in plastic ball grid array (PBGA) package thermal design as they enhance the package performance. Simulation is a versatile design optimization tool for characterizing the thermal vias and balls. However, the finer geometric details of the vias require excessive memory and modeling and simulation time. Different modeling concepts are being tried in the industry to include finer geometries in the package. This paper shows a methodology of developing compact thermal via models and validating the same with detailed models. The accuracy of compact thermal via models with respect to the detailed models has been determined using PBGA 352 as the test vehicle. It is found that the accuracy is within 3%. The simulation models of PBGA 352 have been validated by measurements and found that the accuracy of model is within 10%. Two and four layer PBGA 352s with different via configurations have been characterized with compact thermal via models, and design guidelines for PBGA 352 packages have been obtained.read more
Citations
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Proceedings ArticleDOI
Thermal via placement in 3D ICs
TL;DR: Thermal vias are assigned to specific areas of a 3D IC and used to adjust their effective thermal conductivities and the thermal via placement method makes iterative adjustments to these thermal conductivity in order to achieve a desired maximum temperature objective.
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Placement of thermal vias in 3-D ICs using various thermal objectives
TL;DR: Thermal vias are assigned to specific areas of a 3-D IC and used to adjust their effective-thermal conductivities, and the method efficiently achieves its thermal objective while minimizing the thermal-via utilization.
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3D Floorplanning with Thermal Vias
Eric Wong,Sung Kyu Lim +1 more
TL;DR: This paper presents a thermal via insertion algorithm that can be used to plan thermal via locations during floorplanning that relies on a new thermal analyzer based on random walk techniques.
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Three-dimensional packaging for multi-chip module with through-the-silicon via hole
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Thermal management of a 3D chip stack using a liquid interface to a synthetic jet cooled spreader
TL;DR: In this article, the authors present a unique liquid interface thermal management solution for a 3D chip stack that is embedded within a cavity, in a heat spreader cooled by an array of synthetic jet actuators.
References
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Proceedings ArticleDOI
Optimization of thermal via design parameters based on an analytical thermal resistance model
TL;DR: In this paper, a simple analytical model that provides an efficient approach for analysis of thermal via pads is presented, where small vias close to one another form a cluster with a relatively large dimension.
Proceedings ArticleDOI
Thermal sub-modeling of the wirebonded plastic ball grid array package
TL;DR: In this article, the authors used detailed heat conduction models to characterize the thermal constriction effects of the solder sphere array connecting the plastic ball grid array (PBGA) to the printed wiring board (PWB) and the thermal vias in the PBGA substrate.
Journal ArticleDOI
Thermal strategy for modeling the wirebonded pbga packages
TL;DR: In this paper, thermal analysis of a package and a printed circuit board (PCB) stack-up is performed for a better understanding of package constitutive elements, allowing an enhanced thermal coupling of package and board for cost effective thermal management.