Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods Maximum chip performance under peak permissible temperature limits may be achieved with the help of combined electrical and thermal simulation of VLSI circuits.

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

Nanoscale thermal transport. II. 2003–2012

Abstract: A diverse spectrum of technology drivers such as improved thermal barriers, higher efficiency thermoelectric energy conversion, phase-change memory, heat-assisted magnetic recording, thermal management of nanoscale electronics, and nanoparticles for thermal medical therapies are motivating studies of the applied physics of thermal transport at the nanoscale. This review emphasizes developments in experiment, theory, and computation in the past ten years and summarizes the present status of the field. Interfaces become increasingly important on small length scales. Research during the past decade has extended studies of interfaces between simple metals and inorganic crystals to interfaces with molecular materials and liquids with systematic control of interface chemistry and physics. At separations on the order of ∼1 nm, the science of radiative transport through nanoscale gaps overlaps with thermal conduction by the coupling of electronic and vibrational excitations across weakly bonded or rough interface...

Thermal-induced leakage power optimization by redundant resource allocation

Abstract: Traditionally, at early design stages, leakage power is associated with the number of transistors in a design. Hence, intuitively an implementation with minimum resource usage would be best for low leakage. Such an allocation would generally be followed by switching optimal resource binding to achieve a low power design. This treatment of leakage power is unaware of operating conditions such as temperature. In this paper, we propose a technique to reduce the total leakage power of a design by identifying the optimal number of resources during allocation and binding. We demonstrate that, contrary to the general tendency to minimize the number of resources, the best solution can actually be achieved if a certain degree of redundancy is allowed. This is due to the fact that leakage is strongly dependent on the on-chip temperature profile. Distributing activity over a higher number of resources can reduce power density, remove potential hotspots and subsequently minimize thermal induced leakage. On the other hand, using an arbitrarily high number of resources will not yield the best solution. In this paper, we show that there is a power density, hence, temperature, at which the total leakage power will reach its optimal value. Such an optimal resource number can be a better starting point for the subsequent switching-driven low power binding. We also present a high-level power density-aware leakage model. Based on the estimates by this model, we optimize the total leakage power by 53.8% on average compared to the minimum resource binding, and 35.7% on average compared to a temperature-aware resource binding technique.

Modèles compacts électro-thermiques du premier ordre et considération de bruit pour les circuits 3D

Abstract: L'integration tridimensionnels (3D) ont ete couronnes de succes dans les dispositifs traditionnels pour augmenter la densite logique et reduire les distances de mouvement des donnees. Il resout les limites fondamentales de la mise a l'echelle, par ex. retard croissant dans les interconnexions, les couts de developpement et la variabilite. La plupart des peripheriques de memoire livres aujourd'hui comportent une forme d'empilage de puce. Mais en raison des limites de dissipation de puissance des circuits integres, la frequence de fonctionnement du MPU d'aujourd'hui a ete limitee a quelques GHz. Le but de la these est de fournir une methode de conception globale pour le circuit integre 3D dans le domaine electrique, thermique, electrothermique et aussi le bruit. A cette fin, la question de recherche est la suivante: Comment realiser la conception 3D IC, comment gerer VLS 3D IC et comment resoudre les problemes thermiques dans le CI 3D. Dans ce contexte, les methodes de simulation pour le substrat et egalement la connectivite relative (TSV, RDL, Micro strip et circuits integres dans le substrat) sont proposees. Afin de satisfaire la demande de recherche, un 3D-TLE et une impedance de substrat sont programmes dans Matlab, qui peut automatiquement extraire de tous les contacts; impedance, de forme arbitraire et de matiere arbitraire. L'extracteur est compatible a 100% avec le simulateur de cœur SPICE et verifie avec les resultats de mesure et les resultats de simulation FEM. Et comme pour une demo, une frequence de 26 GHz et un filtre RF de bande passante 2GHz sont proposes dans ce travail. Un autre simulateur electrothermique est egalement programme et verifie avec ADS. En tant que solution a la dissipation thermique locale, le caloduc plat est propose comme composant potentiel. Le modele caloduc est verifie avec une simulation FEM. La methode d'analyse du bruit des substrats et les methodes de calcul de electriques et thermo-mecanique KOZ sont egalement presentees.

Graphene Heat Spreaders for Electronics Thermal Management Applications

Abstract: Graphene shows great potential for applications in electronics due to its outstanding physical properties such as extremely high electron mobility, high thermal conductivity, high Young’s modulus and very high surface-to-volume ratio. Among these attractive properties, the high intrinsic thermal conductivity is a critical advantage for the application of graphene in electronics to alleviate heat dissipation problems. The work described in this thesis attempts to apply graphene as heat spreader for thermal management in electronic packaging. To apply graphene as a potential alternative to metals for heat spreading applications, high-quality material and large-area synthesis is required. In the current thesis work, thermal chemical vapor deposition (TCVD), liquid phase exfoliation (LPE) from graphite, and reduction of graphene ox- ide (GO) are used to synthesize graphene, and transfer methods were also demonstrated. In the TCVD approach, high quality graphene was fabricated over a large- area, controlling the graphene layer thickness. The thermal performance of graphene heat spreaders was evaluated by the temperature drop of the hotspots after the graphene transfer. To further enable the development of graphene heat spreaders, phonon scattering on the graphene-substrate interface, phonon-grain boundary scattering, thermal resistance boundary (TBR), and the effect of the number of graphene layers are discussed. In the LPE approach, following LPE films were made by two different methods, vacuum filtration and drop coating. Three different methods were combined to evaluate and predict the thermal performance of such graphene- based films. Resistance thermometers were used to monitor the hotspot temperature decrease versus the Joule heat flow as a result of using graphene- based heat spreaders. The 3ω method was used to experimentally deter- mine the in-plane and through-plane thermal conductivities of such films. A finite element (FE) model of the hotspot test structure was setup using the in-plane and through-plane thermal conductivities obtained from the 3ω measurements. Simulations were performed to predict the hotspot temperature decrease with excellent agreement obtained between all methods. The results indicate that the alignment and purity of the graphene-based films, as well as their thermal boundary resistance with respect to the chip, are key parameters when determining the thermal performance of graphene-based heat spreaders. In the reduction of GO approach, a graphene-based film heat spreader was fabricated from the reduced graphene oxide (RGO). However, these free- standing materials were poorly adhered to the substrate because only weak van der Waals interactions provide any adhesion. The enhanced heat transfer by introducing alternative heat-escaping channels into a graphene-based film bonded to functionalized graphene oxide through amino-silane molecules is demonstrated. Different techniques such as resistance thermometers, IR test, photothermal reflectance and molecular dynamics simulations were employed to reveal that the functionalization mediates heat transport in graphene nanoflakes. These studies suggest a significant package level solution for the thermal management of hotspots in high-power electronics at the micro- and nanometer scale.

Wattch: a framework for architectural-level power analysis and optimizations

Abstract: Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

Fundamentals of Modern VLSI Devices

Abstract: Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

Dynamic thermal management for high-performance microprocessors

Abstract: With the increasing clock rate and transistor count of today's microprocessors, power dissipation is becoming a critical component of system design complexity. Thermal and power-delivery issues are becoming especially critical for high-performance computing systems. In this work, we investigate dynamic thermal management as a technique to control CPU power dissipation. With the increasing usage of clock gating techniques, the average power dissipation typically seen by common applications is becoming much less than the chip's rated maximum power dissipation. However system designers still must design thermal heat sinks to withstand the worse-case scenario. We define and investigate the major components of any dynamic thermal management scheme. Specifically we explore the tradeoffs between several mechanisms for responding to periods of thermal trauma and we consider the effects of hardware and software implementations. With approximate dynamic thermal management, the CPU can be designed for a much lower maximum power rating, with minimal performance impact for typical applications.

CMOS scaling into the nanometer regime

Abstract: Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.