Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods Maximum chip performance under peak permissible temperature limits may be achieved with the help of combined electrical and thermal simulation of VLSI circuits.
01 Jan 2006-
TL;DR: In this article, the authors present a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power very large scale integration (VLSI) circuits.
Abstract: The growing packing density and power con- sumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers. The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnec- tions. Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues. This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits. The paper is concluded with an over- view of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods.
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3 citations
Dissertation•
01 Jan 2018
TL;DR: In this paper, the authors focused their attention on the thermal property investigation of polycrystalline diamonds (PCDs) and carbon nanotubes (CNTs) for thermal management applications.
Abstract: III Abstract The scaling down of device sizes and the increasing in power dissipation make heat transport and removal a major technological impediment to the future development for electronic applications. Limited heat conduction within devices causes severe localized self-heating problems. Temperature increase significantly degrades the device performance, and the thermal stress caused by the mismatch in the coefficient of thermal expansion shortens the device lifetime drastically. To solve these issues, the development of highly effective heat transfer materials, such as heat sinks, heat spreaders, and thermal interface materials, has received extensive attention. Carbon-based materials, such as carbon nanotubes (CNTs) and diamonds, become attractive for thermal management applications due to their superior thermal properties. In this dissertation, I have focused my attention on the thermal property investigation of polycrystalline diamonds (PCDs) and CNTs for thermal management applications. For the PCD and CNT thermal property investigation, it includes the growth of PCDs and CNTs, the thermal measurement (technique development), the building up of the thermal model, and the thermal conductivity fitting based on the thermal model. Diamonds have been proposed as advanced heat spreaders and heat sinks for high power density devices. Polycrystalline diamond stands out among all diamond isotopes for its versatility, low production cost and high
2 citations
Dissertation•
20 May 2016
TL;DR: Cette these porte sur le theme general de la fiabilite des circuits microelectroniques en passant par trois grandes etapes traduites par les trois parties of ce manuscrit.
Abstract: Cette these porte sur le theme general de la fiabilite des circuits microelectroniques. Le but de notre travail fut de developper un outil de simulation multi-physiques pour la conception des circuits integres fiables qui possede les caracteristiques innovatrices suivantes : • (i) L’integration dans un environnement de conception microelectronique standard, tel que l’environnement Cadence® ; • (ii) La possibilite de simulation, sur de longues durees, du comportement des circuits CMOS analogiques en tenant compte du phenomene de vieillissement ; • (iii) La simulation de plusieurs physiques (electrique-thermique-mecanique) couplees dans ce meme environnement de CAO en utilisant la methode de simulation directe. Ce travail de these a ete realise en passant par trois grandes etapes traduites par les trois parties de ce manuscrit.
1 citations
Dissertation•
07 Apr 2015
1 citations
Journal Article•
TL;DR: Ganatra et al. as mentioned in this paper explored the feasibility of a passive cooling system based on phase change materials (PCMs) for thermal management of mobile devices, which stabilizes temperatures due to the latent heat of phase change thus increasing the operating time of the device before threshold temperatures are exceeded.
Abstract: Ganatra,Yash Yogesh M.S.M.E, Purdue University, December 2016. Passive Thermal Management using Phase Change Materials. Major Professor: Amy Marconnet, School of Mechanical Engineering. The trend of enhanced functionality and reducing thickness of mobile devices has led to a rapid increase in power density and a potential thermal bottleneck since thermal limits of components remain unchanged. Active cooling mechanisms are not feasible due to size, weight and cost constraints. This work explores the feasibility of a passive cooling system based on Phase Change Materials (PCMs) for thermal management of mobile devices. PCMs stabilize temperatures due to the latent heat of phase change thus increasing the operating time of the device before threshold temperatures are exceeded. The primary contribution of this work is the identification of key parameters which influence the design of a PCM based thermal management system from both the experiments and the numerical models. This work first identifies strategies for integrating PCMs in an electronic device. A detailed review of past research, including experimental techniques and computational models, yields key material properties and metrics to evaluate the performance of PCMs. Subsequently, a miniaturized version of a conventional thermal conductivity measurement technique is developed to characterize thermal resistance of PCMs. Further, latent heat and transition temperatures are also characterized for a wide range of PCMs. In-situ measurements with PCMs placed on the processor indicate that some PCMs can extend the operating time of the device by as much as a factor of 2.48 relative to baseline tests (with no PCMs). This increase in operating time is investigated by computational thermal models that explore various integration locations, both at the package and device level.
1 citations
References
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01 May 2000
TL;DR: Wattch is presented, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level and opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.
Abstract: Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.
2,848 citations
Book•
IBM1
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Abstract: Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.
2,680 citations
20 Jan 2001
TL;DR: This work investigates dynamic thermal management as a technique to control CPU power dissipation and explores the tradeoffs between several mechanisms for responding to periods of thermal trauma and the effects of hardware and software implementations.
Abstract: With the increasing clock rate and transistor count of today's microprocessors, power dissipation is becoming a critical component of system design complexity. Thermal and power-delivery issues are becoming especially critical for high-performance computing systems. In this work, we investigate dynamic thermal management as a technique to control CPU power dissipation. With the increasing usage of clock gating techniques, the average power dissipation typically seen by common applications is becoming much less than the chip's rated maximum power dissipation. However system designers still must design thermal heat sinks to withstand the worse-case scenario. We define and investigate the major components of any dynamic thermal management scheme. Specifically we explore the tradeoffs between several mechanisms for responding to periods of thermal trauma and we consider the effects of hardware and software implementations. With approximate dynamic thermal management, the CPU can be designed for a much lower maximum power rating, with minimal performance impact for typical applications.
882 citations
IBM1
TL;DR: In this article, the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations are discussed, including power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays.
Abstract: Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.
861 citations