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Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods Maximum chip performance under peak permissible temperature limits may be achieved with the help of combined electrical and thermal simulation of VLSI circuits.

TL;DR: In this article, the authors present a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power very large scale integration (VLSI) circuits.
Abstract: The growing packing density and power con- sumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers. The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnec- tions. Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues. This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits. The paper is concluded with an over- view of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods.
Citations
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Journal ArticleDOI

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08 Dec 2001-BMJ
TL;DR: There is, I think, something ethereal about i —the square root of minus one, which seems an odd beast at that time—an intruder hovering on the edge of reality.
Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

33,785 citations

01 Jan 2014
TL;DR: In this article, a review of thermal transport at the nanoscale is presented, emphasizing developments in experiment, theory, and computation in the past ten years and summarizes the present status of the field.
Abstract: A diverse spectrum of technology drivers such as improved thermal barriers, higher efficiency thermoelectric energy conversion, phase-change memory, heat-assisted magnetic recording, thermal management of nanoscale electronics, and nanoparticles for thermal medical therapies are motivating studies of the applied physics of thermal transport at the nanoscale. This review emphasizes developments in experiment, theory, and computation in the past ten years and summarizes the present status of the field. Interfaces become increasingly important on small length scales. Research during the past decade has extended studies of interfaces between simple metals and inorganic crystals to interfaces with molecular materials and liquids with systematic control of interface chemistry and physics. At separations on the order of ∼1 nm, the science of radiative transport through nanoscale gaps overlaps with thermal conduction by the coupling of electronic and vibrational excitations across weakly bonded or rough interface...

53 citations

Proceedings ArticleDOI
05 Nov 2006
TL;DR: It is shown that there is a power density, hence, temperature, at which the total leakage power will reach its optimal value, and such an optimal resource number can be a better starting point for the subsequent switching-driven low power binding.
Abstract: Traditionally, at early design stages, leakage power is associated with the number of transistors in a design. Hence, intuitively an implementation with minimum resource usage would be best for low leakage. Such an allocation would generally be followed by switching optimal resource binding to achieve a low power design. This treatment of leakage power is unaware of operating conditions such as temperature. In this paper, we propose a technique to reduce the total leakage power of a design by identifying the optimal number of resources during allocation and binding. We demonstrate that, contrary to the general tendency to minimize the number of resources, the best solution can actually be achieved if a certain degree of redundancy is allowed. This is due to the fact that leakage is strongly dependent on the on-chip temperature profile. Distributing activity over a higher number of resources can reduce power density, remove potential hotspots and subsequently minimize thermal induced leakage. On the other hand, using an arbitrarily high number of resources will not yield the best solution. In this paper, we show that there is a power density, hence, temperature, at which the total leakage power will reach its optimal value. Such an optimal resource number can be a better starting point for the subsequent switching-driven low power binding. We also present a high-level power density-aware leakage model. Based on the estimates by this model, we optimize the total leakage power by 53.8% on average compared to the minimum resource binding, and 35.7% on average compared to a temperature-aware resource binding technique.

21 citations

Dissertation
16 May 2018
TL;DR: In this article, a methode de conception globale for le circuit integre 3D dans le domaine electrique, thermique, electrothermique et aussi le bruit is presented.
Abstract: L'integration tridimensionnels (3D) ont ete couronnes de succes dans les dispositifs traditionnels pour augmenter la densite logique et reduire les distances de mouvement des donnees. Il resout les limites fondamentales de la mise a l'echelle, par ex. retard croissant dans les interconnexions, les couts de developpement et la variabilite. La plupart des peripheriques de memoire livres aujourd'hui comportent une forme d'empilage de puce. Mais en raison des limites de dissipation de puissance des circuits integres, la frequence de fonctionnement du MPU d'aujourd'hui a ete limitee a quelques GHz. Le but de la these est de fournir une methode de conception globale pour le circuit integre 3D dans le domaine electrique, thermique, electrothermique et aussi le bruit. A cette fin, la question de recherche est la suivante: Comment realiser la conception 3D IC, comment gerer VLS 3D IC et comment resoudre les problemes thermiques dans le CI 3D. Dans ce contexte, les methodes de simulation pour le substrat et egalement la connectivite relative (TSV, RDL, Micro strip et circuits integres dans le substrat) sont proposees. Afin de satisfaire la demande de recherche, un 3D-TLE et une impedance de substrat sont programmes dans Matlab, qui peut automatiquement extraire de tous les contacts; impedance, de forme arbitraire et de matiere arbitraire. L'extracteur est compatible a 100% avec le simulateur de cœur SPICE et verifie avec les resultats de mesure et les resultats de simulation FEM. Et comme pour une demo, une frequence de 26 GHz et un filtre RF de bande passante 2GHz sont proposes dans ce travail. Un autre simulateur electrothermique est egalement programme et verifie avec ADS. En tant que solution a la dissipation thermique locale, le caloduc plat est propose comme composant potentiel. Le modele caloduc est verifie avec une simulation FEM. La methode d'analyse du bruit des substrats et les methodes de calcul de electriques et thermo-mecanique KOZ sont egalement presentees.

6 citations

Dissertation
01 Jan 2016
TL;DR: In this paper, thermal chemical vapor deposition (TCVD), liquid phase exfoliation (LPE) from graphite, and reduction of graphene ox- ide (GO) were used to synthesize graphene, and transfer methods were also demonstrated.
Abstract: Graphene shows great potential for applications in electronics due to its outstanding physical properties such as extremely high electron mobility, high thermal conductivity, high Young’s modulus and very high surface-to-volume ratio. Among these attractive properties, the high intrinsic thermal conductivity is a critical advantage for the application of graphene in electronics to alleviate heat dissipation problems. The work described in this thesis attempts to apply graphene as heat spreader for thermal management in electronic packaging. To apply graphene as a potential alternative to metals for heat spreading applications, high-quality material and large-area synthesis is required. In the current thesis work, thermal chemical vapor deposition (TCVD), liquid phase exfoliation (LPE) from graphite, and reduction of graphene ox- ide (GO) are used to synthesize graphene, and transfer methods were also demonstrated. In the TCVD approach, high quality graphene was fabricated over a large- area, controlling the graphene layer thickness. The thermal performance of graphene heat spreaders was evaluated by the temperature drop of the hotspots after the graphene transfer. To further enable the development of graphene heat spreaders, phonon scattering on the graphene-substrate interface, phonon-grain boundary scattering, thermal resistance boundary (TBR), and the effect of the number of graphene layers are discussed. In the LPE approach, following LPE films were made by two different methods, vacuum filtration and drop coating. Three different methods were combined to evaluate and predict the thermal performance of such graphene- based films. Resistance thermometers were used to monitor the hotspot temperature decrease versus the Joule heat flow as a result of using graphene- based heat spreaders. The 3ω method was used to experimentally deter- mine the in-plane and through-plane thermal conductivities of such films. A finite element (FE) model of the hotspot test structure was setup using the in-plane and through-plane thermal conductivities obtained from the 3ω measurements. Simulations were performed to predict the hotspot temperature decrease with excellent agreement obtained between all methods. The results indicate that the alignment and purity of the graphene-based films, as well as their thermal boundary resistance with respect to the chip, are key parameters when determining the thermal performance of graphene-based heat spreaders. In the reduction of GO approach, a graphene-based film heat spreader was fabricated from the reduced graphene oxide (RGO). However, these free- standing materials were poorly adhered to the substrate because only weak van der Waals interactions provide any adhesion. The enhanced heat transfer by introducing alternative heat-escaping channels into a graphene-based film bonded to functionalized graphene oxide through amino-silane molecules is demonstrated. Different techniques such as resistance thermometers, IR test, photothermal reflectance and molecular dynamics simulations were employed to reveal that the functionalization mediates heat transport in graphene nanoflakes. These studies suggest a significant package level solution for the thermal management of hotspots in high-power electronics at the micro- and nanometer scale.

6 citations

References
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Proceedings ArticleDOI
09 Aug 2004
TL;DR: A probabilistic framework for full-chip estimation of subthreshold leakage power distribution considering both within-die and die-to-die variations in process (P), temperature (T) and supply voltage (V) is presented.
Abstract: This paper presents a probabilistic framework for full-chip estimation of subthreshold leakage power distribution considering both within-die and die-to-die variations in process (P), temperature (T) and supply voltage (V). The results obtained under this framework are compared to BSIM results and are found to be more accurate in comparison to those obtained from existing statistical models. Using this framework, a quantitative analysis of the relative sensitivities of subthreshold leakage to P-T-V variations has been presented. For the first time, the effects of die-to-die channel length and temperature variations on subthreshold leakage are studied in combination with all within-die variations. It has been shown that for accurate estimation of subthreshold leakage, it is important to consider die-to-die temperature variations which can significantly increase the leakage power due to electrothermal couplings between power and temperature. Furthermore, the full-chip leakage power distribution arising due to both within-die and die-to-die P-T-V is calculated, which is subsequently used to estimate the leakage constrained yield under the impact of these variations. The calculations show that the yield is significantly lowered under the impact of within-die and die-to-die process and temperature variations.

59 citations

Proceedings ArticleDOI
22 Mar 2004
TL;DR: A method of SPICE-compatible thermal simulation for interconnect reliability analysis is proposed and the improved extended Krylov subspace (IEKS) method, independent of the number of input ports, is used for thermal simulation.
Abstract: With the growing power dissipation in modem high performance VLSI designs, nonuniform temperature distribution and limited heat-conduction capability have caused thermal induced performance and reliability degradation. However the problem modeled by finite difference method for interconnect reliability analysis has huge size if we require the resolution with wire width. In addition, the generated lumped circuit has significant number of input sources, and the bottleneck of traditional model reduction methods is the big number of input ports. In this paper we propose a method of SPICE-compatible thermal simulation for interconnect reliability analysis. The lumped thermal circuit modeling with adaptive approach is used to reduce the problem size. The improved extended Krylov subspace (IEKS) method, independent of the number of input ports, is used for thermal simulation. The experimental results show that our method provides highly accurate results with performance improvement 15 x over T-Spice for the problem with node number 72428.

56 citations

Journal ArticleDOI
07 Feb 1995
TL;DR: In this paper, a transient three-dimensional analysis was performed for passive thermal control of a plastic quad flat package (PQFP) by incorporating phase change material (PCM) under the printed wiring board (PWB).
Abstract: A transient three-dimensional analysis was performed for passive thermal control of a plastic quad flat package (PQFP) by incorporating phase change material (PCM) under the printed wiring board (PWB). Governing conservation equations for mass, momentum and energy were solved by an implicit finite volume numerical technique. The effects of phase change were modelled by a single domain enthalpy-porosity technique. To study the effects of thermal conductivity of the board, a total of four cases were considered with two different board materials. It was found that passive cooling with PCM can arrest the temperature rise for a substantial time, for the power level considered. A higher board thermal conductivity resulted in a reduction in temperature levels. The melt region for a lower thermal conductivity of the board was found to be localized near the package footprint, while, for a higher board conductivity, the melt region extends along the board.

56 citations

Journal ArticleDOI
TL;DR: In this paper, the authors describe how electromigration is a ticking time bomb in IC designs, which can trigger a system failure at some undefined future time, particularly likely to afflict the thin, tightly spaced power-distribution lines of deep-submicron designs.
Abstract: Electromigration results from the movement of metal ions as current flows through power wires in integrated circuits, causing voids and hillocks in the wires. The voids increase resistance or even cause opens in the wires, while hillocks can cause shorts to adjacent wires. This paper describes how electromigration is a ticking time bomb in IC designs, which can trigger a system failure at some undefined future time. The phenomenon is particularly likely to afflict the thin, tightly spaced power-distribution lines of deep-submicron designs.

43 citations

Journal ArticleDOI
TL;DR: A system capable of modeling VLSI effects in a realistic and sufficiently accurate way that uses a reasonable amount of CPU resources is presented and an innovative solver is proposed.
Abstract: Needs for electro-thermal simulation of VLSI circuits, as opposed to both the system and device levels, are analyzed. A system capable of modeling these effects in a realistic and sufficiently accurate way that uses a reasonable amount of CPU resources is presented. An innovative solver is also proposed. The system is used to study the importance of some three dimensional (3-D) effects as well as metallic connections. A complete example was treated to have an insight on the type of results to be expected and the corresponding costs in terms of CPU.

42 citations