Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods Maximum chip performance under peak permissible temperature limits may be achieved with the help of combined electrical and thermal simulation of VLSI circuits.
01 Jan 2006-
TL;DR: In this article, the authors present a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power very large scale integration (VLSI) circuits.
Abstract: The growing packing density and power con- sumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers. The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnec- tions. Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues. This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits. The paper is concluded with an over- view of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods.
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TL;DR: There is, I think, something ethereal about i —the square root of minus one, which seems an odd beast at that time—an intruder hovering on the edge of reality.
Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.
Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …
33,785 citations
University of Illinois at Urbana–Champaign1, Massachusetts Institute of Technology2, Harvard University3, Stanford University4, Rensselaer Polytechnic Institute5, Pennsylvania State University6, University of California, Berkeley7, Brown University8, University of Florida9, University of Texas at Austin10
TL;DR: In this article, a review of thermal transport at the nanoscale is presented, emphasizing developments in experiment, theory, and computation in the past ten years and summarizes the present status of the field.
Abstract: A diverse spectrum of technology drivers such as improved thermal barriers, higher efficiency thermoelectric energy conversion, phase-change memory, heat-assisted magnetic recording, thermal management of nanoscale electronics, and nanoparticles for thermal medical therapies are motivating studies of the applied physics of thermal transport at the nanoscale. This review emphasizes developments in experiment, theory, and computation in the past ten years and summarizes the present status of the field. Interfaces become increasingly important on small length scales. Research during the past decade has extended studies of interfaces between simple metals and inorganic crystals to interfaces with molecular materials and liquids with systematic control of interface chemistry and physics. At separations on the order of ∼1 nm, the science of radiative transport through nanoscale gaps overlaps with thermal conduction by the coupling of electronic and vibrational excitations across weakly bonded or rough interface...
53 citations
05 Nov 2006
TL;DR: It is shown that there is a power density, hence, temperature, at which the total leakage power will reach its optimal value, and such an optimal resource number can be a better starting point for the subsequent switching-driven low power binding.
Abstract: Traditionally, at early design stages, leakage power is associated with the number of transistors in a design. Hence, intuitively an implementation with minimum resource usage would be best for low leakage. Such an allocation would generally be followed by switching optimal resource binding to achieve a low power design. This treatment of leakage power is unaware of operating conditions such as temperature. In this paper, we propose a technique to reduce the total leakage power of a design by identifying the optimal number of resources during allocation and binding. We demonstrate that, contrary to the general tendency to minimize the number of resources, the best solution can actually be achieved if a certain degree of redundancy is allowed. This is due to the fact that leakage is strongly dependent on the on-chip temperature profile. Distributing activity over a higher number of resources can reduce power density, remove potential hotspots and subsequently minimize thermal induced leakage. On the other hand, using an arbitrarily high number of resources will not yield the best solution. In this paper, we show that there is a power density, hence, temperature, at which the total leakage power will reach its optimal value. Such an optimal resource number can be a better starting point for the subsequent switching-driven low power binding. We also present a high-level power density-aware leakage model. Based on the estimates by this model, we optimize the total leakage power by 53.8% on average compared to the minimum resource binding, and 35.7% on average compared to a temperature-aware resource binding technique.
21 citations
Dissertation•
16 May 2018
TL;DR: In this article, a methode de conception globale for le circuit integre 3D dans le domaine electrique, thermique, electrothermique et aussi le bruit is presented.
Abstract: L'integration tridimensionnels (3D) ont ete couronnes de succes dans les dispositifs traditionnels pour augmenter la densite logique et reduire les distances de mouvement des donnees. Il resout les limites fondamentales de la mise a l'echelle, par ex. retard croissant dans les interconnexions, les couts de developpement et la variabilite. La plupart des peripheriques de memoire livres aujourd'hui comportent une forme d'empilage de puce. Mais en raison des limites de dissipation de puissance des circuits integres, la frequence de fonctionnement du MPU d'aujourd'hui a ete limitee a quelques GHz. Le but de la these est de fournir une methode de conception globale pour le circuit integre 3D dans le domaine electrique, thermique, electrothermique et aussi le bruit. A cette fin, la question de recherche est la suivante: Comment realiser la conception 3D IC, comment gerer VLS 3D IC et comment resoudre les problemes thermiques dans le CI 3D. Dans ce contexte, les methodes de simulation pour le substrat et egalement la connectivite relative (TSV, RDL, Micro strip et circuits integres dans le substrat) sont proposees. Afin de satisfaire la demande de recherche, un 3D-TLE et une impedance de substrat sont programmes dans Matlab, qui peut automatiquement extraire de tous les contacts; impedance, de forme arbitraire et de matiere arbitraire. L'extracteur est compatible a 100% avec le simulateur de cœur SPICE et verifie avec les resultats de mesure et les resultats de simulation FEM. Et comme pour une demo, une frequence de 26 GHz et un filtre RF de bande passante 2GHz sont proposes dans ce travail. Un autre simulateur electrothermique est egalement programme et verifie avec ADS. En tant que solution a la dissipation thermique locale, le caloduc plat est propose comme composant potentiel. Le modele caloduc est verifie avec une simulation FEM. La methode d'analyse du bruit des substrats et les methodes de calcul de electriques et thermo-mecanique KOZ sont egalement presentees.
6 citations
Dissertation•
01 Jan 2016
TL;DR: In this paper, thermal chemical vapor deposition (TCVD), liquid phase exfoliation (LPE) from graphite, and reduction of graphene ox- ide (GO) were used to synthesize graphene, and transfer methods were also demonstrated.
Abstract: Graphene shows great potential for applications in electronics due to its outstanding physical properties such as extremely high electron mobility, high thermal conductivity, high Young’s modulus and very high surface-to-volume ratio. Among these attractive properties, the high intrinsic thermal conductivity is a critical advantage for the application of graphene in electronics to alleviate heat dissipation problems. The work described in this thesis attempts to apply graphene as heat spreader for thermal management in electronic packaging.
To apply graphene as a potential alternative to metals for heat spreading applications, high-quality material and large-area synthesis is required. In the current thesis work, thermal chemical vapor deposition (TCVD), liquid phase exfoliation (LPE) from graphite, and reduction of graphene ox- ide (GO) are used to synthesize graphene, and transfer methods were also demonstrated.
In the TCVD approach, high quality graphene was fabricated over a large- area, controlling the graphene layer thickness. The thermal performance of graphene heat spreaders was evaluated by the temperature drop of the hotspots after the graphene transfer. To further enable the development of graphene heat spreaders, phonon scattering on the graphene-substrate interface, phonon-grain boundary scattering, thermal resistance boundary (TBR), and the effect of the number of graphene layers are discussed.
In the LPE approach, following LPE films were made by two different methods, vacuum filtration and drop coating. Three different methods were combined to evaluate and predict the thermal performance of such graphene- based films. Resistance thermometers were used to monitor the hotspot temperature decrease versus the Joule heat flow as a result of using graphene- based heat spreaders. The 3ω method was used to experimentally deter- mine the in-plane and through-plane thermal conductivities of such films. A finite element (FE) model of the hotspot test structure was setup using the in-plane and through-plane thermal conductivities obtained from the 3ω measurements. Simulations were performed to predict the hotspot temperature decrease with excellent agreement obtained between all methods. The results indicate that the alignment and purity of the graphene-based films, as well as their thermal boundary resistance with respect to the chip, are key parameters when determining the thermal performance of graphene-based heat spreaders.
In the reduction of GO approach, a graphene-based film heat spreader was fabricated from the reduced graphene oxide (RGO). However, these free- standing materials were poorly adhered to the substrate because only weak van der Waals interactions provide any adhesion. The enhanced heat transfer by introducing alternative heat-escaping channels into a graphene-based film bonded to functionalized graphene oxide through amino-silane molecules is demonstrated. Different techniques such as resistance thermometers, IR test, photothermal reflectance and molecular dynamics simulations were employed to reveal that the functionalization mediates heat transport in graphene nanoflakes. These studies suggest a significant package level solution for the thermal management of hotspots in high-power electronics at the micro- and nanometer scale.
6 citations
References
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TL;DR: In this paper, the effect of temperature-dependent thermal conductivity is included through application of the Kirchhoff transformation, and the condition of uniform temperature on the bottom surface, which is in contact with the solder layer, is studied when cooling is by convection.
Abstract: Graphs to facilitate calculation of steady-state peak temperature at transistor sites on chips are presented. The effect of temperature-dependent thermal conductivity is included through application of the Kirchhoff transformation. The Green's function solution method is used to evaluate the temperature field. The condition of uniform temperature on the bottom surface, which is in contact with the solder layer, is studied when cooling is by convection. This assists the linearization of working formulas for temperature-dependent thermal conductivity of materials such as Si, InP, and GaAs in the presence of convective cooling, as well as prescribed bottom surface temperature. >
39 citations
TL;DR: The new method first constructs a reduced but electrically equivalent P/G network, then the sequence of linear programming method is applied to optimize the reduced network, and the solution of the original network is then backsolved from the optimized reduced network.
Abstract: We present an efficient method of minimizing the area of power/ground (P/G) networks in integrated circuit layouts subject to reliability constraints. Instead of directly sizing the original P/G network extracted from a circuit layout, as done previously, the new method first constructs a reduced but electrically equivalent P/G network. Then the sequence of linear programming method is applied to optimize the reduced network. The solution of the original network is then backsolved from the optimized reduced network. The new method exploits the regularities in the P/G networks to reduce the complexities of P/G networks. Experimental results show that the sizes of reduced networks are typically significantly smaller than that of the original networks. The resulting algorithm is fast enough that P/G networks with more than one million branches can be sized in a few minutes on modern Sun workstations.
33 citations
08 Aug 2005
TL;DR: Experimental results showed that a 25% reduction in the total system energy can be achieved compared to the optimal component-level DPM policy.
Abstract: This paper presented a hierarchical power management architecture which aims to facilitate power-awareness in an energy-managed computer (EMC) system with multiple components. The proposed architecture divides PM function into two layers: system-level and component-level. The system-level hierarchical PM was formulated as a concurrent service request flow regulation and application scheduling problem. Experimental results showed that a 25% reduction in the total system energy can be achieved compared to the optimal component-level DPM policy.
31 citations
16 Feb 2004
TL;DR: In this paper, a thermal-aware power-delivery optimization algorithm was proposed to achieve high power supply quality and thermal reliability by simultaneously considering thermal and power integrity in VLSI designs.
Abstract: With the increasing power density and heat-dissipation cost of modern VLSI designs, thermal and power integrity has become serious concern. Although the impacts of thermal effects on transistor and interconnect performance are well-studied, the interactions between power-delivery and thermal effects are not clear. As a result, power-delivery design without thermal consideration may cause soft-error, reliability degradation, and even premature chip failures. In this paper, we propose a thermal-aware power-delivery optimization algorithm. By simultaneously considering thermal and power integrity, we are able to achieve high power supply quality and thermal reliability. For a 58/spl times/72 mesh as shown in the experimental results, our algorithm shows that the lifetime of the optimized ground network is 9.5 years. Whereas the lifetime of the ground network generated by a traditional method is only 2 years without thermal concern.
30 citations
TL;DR: A slight floorplan modification using the proposed procedure improves on-chip thermal gradient significantly and the maximum temperature difference increases with higher memory area occupancy and the difference is very floorplan sensitive.
Abstract: This paper quantitatively analyzes thermal gradient of SoC and proposes a thermal flattening procedure. First, the impact of dominant parameters, such as area occupancy of memory/logic block, power density, and floorplan on thermal gradient are studied quantitatively. Temperature difference is also evaluated from timing and reliability standpoints. Important results obtained here are 1) the maximum temperature difference increases with higher memory area occupancy and 2) the difference is very floorplan sensitive. Then, we propose a procedure to amend thermal gradient. A slight floorplan modification using the proposed procedure improves on-chip thermal gradient significantly.
29 citations