Open Access
Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods Maximum chip performance under peak permissible temperature limits may be achieved with the help of combined electrical and thermal simulation of VLSI circuits.
Massoud Pedram,Shahin Nazarian +1 more
Reads0
Chats0
TLDR
In this article, the authors present a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power very large scale integration (VLSI) circuits.Abstract:
The growing packing density and power con- sumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers. The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnec- tions. Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues. This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits. The paper is concluded with an over- view of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods.read more
Citations
More filters
Journal ArticleDOI
I and i
TL;DR: There is, I think, something ethereal about i —the square root of minus one, which seems an odd beast at that time—an intruder hovering on the edge of reality.
Nanoscale thermal transport. II. 2003–2012
David G. Cahill,Paul V. Braun,Gang Chen,David R. Clarke,Shanhui Fan,Kenneth E. Goodson,Pawel Keblinski,William P. King,Gerald D. Mahan,Arun Majumdar,Humphrey J. Maris,Simon R. Phillpot,Eric Pop,Li Shi +13 more
TL;DR: In this article, a review of thermal transport at the nanoscale is presented, emphasizing developments in experiment, theory, and computation in the past ten years and summarizes the present status of the field.
Proceedings ArticleDOI
Thermal-induced leakage power optimization by redundant resource allocation
Min Ni,Seda Ogrenci Memik +1 more
TL;DR: It is shown that there is a power density, hence, temperature, at which the total leakage power will reach its optimal value, and such an optimal resource number can be a better starting point for the subsequent switching-driven low power binding.
Dissertation
Modèles compacts électro-thermiques du premier ordre et considération de bruit pour les circuits 3D
TL;DR: In this article, a methode de conception globale for le circuit integre 3D dans le domaine electrique, thermique, electrothermique et aussi le bruit is presented.
Dissertation
Graphene Heat Spreaders for Electronics Thermal Management Applications
TL;DR: In this paper, thermal chemical vapor deposition (TCVD), liquid phase exfoliation (LPE) from graphite, and reduction of graphene ox- ide (GO) were used to synthesize graphene, and transfer methods were also demonstrated.
References
More filters
Proceedings ArticleDOI
Determining the Optimal Timeout Values for a Power-Managed System based on the Theory of Markovian Processes: Offline and Online Algorithms
Peng Rong,Massoud Pedram +1 more
TL;DR: This paper presents a timeout-driven DPM technique which relies on the theory of Markovian processes to determine the energy-optimal timeout values for a system with multiple power saving states while satisfying a set of user defined performance constraints.
Proceedings ArticleDOI
Power supply optimization in sub-130 nm leakage dominant technologies
TL;DR: This paper shows that for 90 nm and 65 nm technologies where leakage power represents a significant fraction of the total power dissipation, Optimum V/sub DD/ is lower than the ITRS specified supply voltage.
Proceedings ArticleDOI
VGTA: variation-aware gate timing analysis
TL;DR: This paper presents an approach to approximate variational RC-/spl pi/ load by using a canonical first-order model, and proposes a new framework to handle the variation-aware gate timing analysis in block-based /spl sigma/TA.
Proceedings ArticleDOI
Efficient transient electrothermal simulation of CMOS VLSI circuits under electrical overstress
TL;DR: In this paper, an efficient transient electrothermal simulator that is built upon a SPICE-like engine is presented, where the transient device temperature is estimated by the convolution of the device power dissipation and its thermal impulse response which can be derived an analytical solution of the heat diffusion equation.
Proceedings ArticleDOI
Dislocation based mechanisms in electromigration
TL;DR: In this article, the role of dislocation dynamics in electromigration degradation is presented based on both theoretical models and experimental data Interactions between high current densities and dislocations were studied using micromechanics measurements, in situ scanning electron microscopy, and transmission electron microscope.
Related Papers (5)
An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management
Sheng-Chih Lin,Kaustav Banerjee +1 more