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Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods Maximum chip performance under peak permissible temperature limits may be achieved with the help of combined electrical and thermal simulation of VLSI circuits.

TL;DR: In this article, the authors present a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power very large scale integration (VLSI) circuits.
Abstract: The growing packing density and power con- sumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers. The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnec- tions. Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues. This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits. The paper is concluded with an over- view of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods.
Citations
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Journal ArticleDOI

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08 Dec 2001-BMJ
TL;DR: There is, I think, something ethereal about i —the square root of minus one, which seems an odd beast at that time—an intruder hovering on the edge of reality.
Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

33,785 citations

01 Jan 2014
TL;DR: In this article, a review of thermal transport at the nanoscale is presented, emphasizing developments in experiment, theory, and computation in the past ten years and summarizes the present status of the field.
Abstract: A diverse spectrum of technology drivers such as improved thermal barriers, higher efficiency thermoelectric energy conversion, phase-change memory, heat-assisted magnetic recording, thermal management of nanoscale electronics, and nanoparticles for thermal medical therapies are motivating studies of the applied physics of thermal transport at the nanoscale. This review emphasizes developments in experiment, theory, and computation in the past ten years and summarizes the present status of the field. Interfaces become increasingly important on small length scales. Research during the past decade has extended studies of interfaces between simple metals and inorganic crystals to interfaces with molecular materials and liquids with systematic control of interface chemistry and physics. At separations on the order of ∼1 nm, the science of radiative transport through nanoscale gaps overlaps with thermal conduction by the coupling of electronic and vibrational excitations across weakly bonded or rough interface...

53 citations

Proceedings ArticleDOI
05 Nov 2006
TL;DR: It is shown that there is a power density, hence, temperature, at which the total leakage power will reach its optimal value, and such an optimal resource number can be a better starting point for the subsequent switching-driven low power binding.
Abstract: Traditionally, at early design stages, leakage power is associated with the number of transistors in a design. Hence, intuitively an implementation with minimum resource usage would be best for low leakage. Such an allocation would generally be followed by switching optimal resource binding to achieve a low power design. This treatment of leakage power is unaware of operating conditions such as temperature. In this paper, we propose a technique to reduce the total leakage power of a design by identifying the optimal number of resources during allocation and binding. We demonstrate that, contrary to the general tendency to minimize the number of resources, the best solution can actually be achieved if a certain degree of redundancy is allowed. This is due to the fact that leakage is strongly dependent on the on-chip temperature profile. Distributing activity over a higher number of resources can reduce power density, remove potential hotspots and subsequently minimize thermal induced leakage. On the other hand, using an arbitrarily high number of resources will not yield the best solution. In this paper, we show that there is a power density, hence, temperature, at which the total leakage power will reach its optimal value. Such an optimal resource number can be a better starting point for the subsequent switching-driven low power binding. We also present a high-level power density-aware leakage model. Based on the estimates by this model, we optimize the total leakage power by 53.8% on average compared to the minimum resource binding, and 35.7% on average compared to a temperature-aware resource binding technique.

21 citations

Dissertation
16 May 2018
TL;DR: In this article, a methode de conception globale for le circuit integre 3D dans le domaine electrique, thermique, electrothermique et aussi le bruit is presented.
Abstract: L'integration tridimensionnels (3D) ont ete couronnes de succes dans les dispositifs traditionnels pour augmenter la densite logique et reduire les distances de mouvement des donnees. Il resout les limites fondamentales de la mise a l'echelle, par ex. retard croissant dans les interconnexions, les couts de developpement et la variabilite. La plupart des peripheriques de memoire livres aujourd'hui comportent une forme d'empilage de puce. Mais en raison des limites de dissipation de puissance des circuits integres, la frequence de fonctionnement du MPU d'aujourd'hui a ete limitee a quelques GHz. Le but de la these est de fournir une methode de conception globale pour le circuit integre 3D dans le domaine electrique, thermique, electrothermique et aussi le bruit. A cette fin, la question de recherche est la suivante: Comment realiser la conception 3D IC, comment gerer VLS 3D IC et comment resoudre les problemes thermiques dans le CI 3D. Dans ce contexte, les methodes de simulation pour le substrat et egalement la connectivite relative (TSV, RDL, Micro strip et circuits integres dans le substrat) sont proposees. Afin de satisfaire la demande de recherche, un 3D-TLE et une impedance de substrat sont programmes dans Matlab, qui peut automatiquement extraire de tous les contacts; impedance, de forme arbitraire et de matiere arbitraire. L'extracteur est compatible a 100% avec le simulateur de cœur SPICE et verifie avec les resultats de mesure et les resultats de simulation FEM. Et comme pour une demo, une frequence de 26 GHz et un filtre RF de bande passante 2GHz sont proposes dans ce travail. Un autre simulateur electrothermique est egalement programme et verifie avec ADS. En tant que solution a la dissipation thermique locale, le caloduc plat est propose comme composant potentiel. Le modele caloduc est verifie avec une simulation FEM. La methode d'analyse du bruit des substrats et les methodes de calcul de electriques et thermo-mecanique KOZ sont egalement presentees.

6 citations

Dissertation
01 Jan 2016
TL;DR: In this paper, thermal chemical vapor deposition (TCVD), liquid phase exfoliation (LPE) from graphite, and reduction of graphene ox- ide (GO) were used to synthesize graphene, and transfer methods were also demonstrated.
Abstract: Graphene shows great potential for applications in electronics due to its outstanding physical properties such as extremely high electron mobility, high thermal conductivity, high Young’s modulus and very high surface-to-volume ratio. Among these attractive properties, the high intrinsic thermal conductivity is a critical advantage for the application of graphene in electronics to alleviate heat dissipation problems. The work described in this thesis attempts to apply graphene as heat spreader for thermal management in electronic packaging. To apply graphene as a potential alternative to metals for heat spreading applications, high-quality material and large-area synthesis is required. In the current thesis work, thermal chemical vapor deposition (TCVD), liquid phase exfoliation (LPE) from graphite, and reduction of graphene ox- ide (GO) are used to synthesize graphene, and transfer methods were also demonstrated. In the TCVD approach, high quality graphene was fabricated over a large- area, controlling the graphene layer thickness. The thermal performance of graphene heat spreaders was evaluated by the temperature drop of the hotspots after the graphene transfer. To further enable the development of graphene heat spreaders, phonon scattering on the graphene-substrate interface, phonon-grain boundary scattering, thermal resistance boundary (TBR), and the effect of the number of graphene layers are discussed. In the LPE approach, following LPE films were made by two different methods, vacuum filtration and drop coating. Three different methods were combined to evaluate and predict the thermal performance of such graphene- based films. Resistance thermometers were used to monitor the hotspot temperature decrease versus the Joule heat flow as a result of using graphene- based heat spreaders. The 3ω method was used to experimentally deter- mine the in-plane and through-plane thermal conductivities of such films. A finite element (FE) model of the hotspot test structure was setup using the in-plane and through-plane thermal conductivities obtained from the 3ω measurements. Simulations were performed to predict the hotspot temperature decrease with excellent agreement obtained between all methods. The results indicate that the alignment and purity of the graphene-based films, as well as their thermal boundary resistance with respect to the chip, are key parameters when determining the thermal performance of graphene-based heat spreaders. In the reduction of GO approach, a graphene-based film heat spreader was fabricated from the reduced graphene oxide (RGO). However, these free- standing materials were poorly adhered to the substrate because only weak van der Waals interactions provide any adhesion. The enhanced heat transfer by introducing alternative heat-escaping channels into a graphene-based film bonded to functionalized graphene oxide through amino-silane molecules is demonstrated. Different techniques such as resistance thermometers, IR test, photothermal reflectance and molecular dynamics simulations were employed to reveal that the functionalization mediates heat transport in graphene nanoflakes. These studies suggest a significant package level solution for the thermal management of hotspots in high-power electronics at the micro- and nanometer scale.

6 citations

References
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Journal ArticleDOI
TL;DR: A design methodology for controlling the switching times of the output drivers to minimize the ground bounce and a closed form expression for the peak value of the differential-mode component of the ground bounces in terms of the on-chip decoupling capacitor are provided.
Abstract: This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics. Next the effect of ground bounce on the propagation delay and the optimum tapering factor of a multistage buffer is discussed and a mathematical relationship for total propagation delay in the presence of the ground bounce is obtained. Effect of an on-chip decoupling capacitor on the ground bounce waveform and circuit speed is analyzed next and a closed form expression for the peak value of the differential-mode component of the ground bounce in terms of the on-chip decoupling capacitor is provided. Finally, a design methodology for controlling the switching times of the output drivers to minimize the ground bounce is presented.

122 citations

Journal ArticleDOI
TL;DR: Experimental results show that the power management method based on a Markov decision process outperforms heuristic methods by as much as 44% in terms of power dissipation savings for a given level of system performance.
Abstract: The goal of a dynamic power management policy is to reduce the power consumption of an electronic system by putting system components into different states, each representing a certain performance and power consumption level. The policy determines the type and timing of these transitions based on the system history, workload, and performance constraints. In this paper we propose a new abstract model of a power-managed electronic system. We formulate the problem of system-level power management as a controlled optimization problem based on the theories of continuous-time Markov derision processes and stochastic networks. This problem is solved exactly using linear programming or heuristically using "policy iteration." Our method is compared with existing heuristic methods for different workload statistics. Experimental results show that the power management method based on a Markov decision process outperforms heuristic methods by as much as 44% in terms of power dissipation savings for a given level of system performance.

110 citations

Proceedings ArticleDOI
04 Nov 2001
TL;DR: It is shown that the effectiveness of vias in reducing the temperature rise in interconnects is highly dependent on the via separation and the dielectric materials used, and the possibility that, under the impact of thermal effects, the performance improvement expected from the use of low-k dielectrics may be degraded.
Abstract: This paper presents both compact analytical models and fast SPICE based 3-D electro-thermal simulation methodology to characterize thermal effects due to Joule heating in high performance Cu/low-k interconnects under steady-state and transient stress conditions. The results demonstrate excellent agreement with experimental data and those using Finite Element (FE) thermal simulations (ANSYS). The effect of vias, as additional heat sinking paths to alleviate the temp erature rise in the metal wires, is included in our analysis to provide more accurate and realistic thermal diagnosis. It shows that the effectiveness of vias in reducing the temperature rise in interconnects is highly dependent on the via separation and the dielectric materials used. The analytical model is then applied to estimate the temperature distribution in multi-level interconnects. In addition, we discuss the possibility that, under the impact of thermal effects, the performance improvement expected from the use of low-k dielectric materials may be degraded. Furthermore, thermal coupling between wires is evaluated and found to be significant. Finally, the impact of metal wire aspect ratio on interconnect thermal characteristics is discussed.

105 citations

Journal ArticleDOI
01 May 2005
TL;DR: An integrated disk drive model is presented that captures the close relationships between capacity, performance and thermal characteristics over time and quantifies the drop off in IDR growth rates over the next decade if the authors are to adhere to the thermal envelope of drive design.
Abstract: The importance of pushing the performance envelope of disk drives continues to grow, not just in the server market but also in numerous consumer electronics products. One of the most fundamental factors impacting disk drive design is the heat dissipation and its effect on drive reliability, since high temperatures can cause off-track errors, or even head crashes. Until now, drive manufacturers have continued to meet the 40% annual growth target of the internal data rates (IDR) by increasing RPMs, and shrinking platter sizes, both of which have counter-acting effects on the heat dissipation within a drive. As this paper will show, we are getting to a point where it is becoming very difficult to stay on this roadmap. This paper presents an integrated disk drive model that captures the close relationships between capacity, performance and thermal characteristics over time. Using this model, we quantify the drop off in IDR growth rates over the next decade if we are to adhere to the thermal envelope of drive design.We present two mechanisms for buying back some of this IDR loss with Dynamic Thermal Management (DTM). The first DTM technique exploits any available thermal slack, between what the drive was intended to support and the currently lower operating temperature, to ramp up the RPM. The second DTM technique assumes that the drive is only designed for average case behavior, thus allowing higher RPMs than the thermal envelope, and employs dynamic throttling of disk drive activities to remain within this envelope.

104 citations

Proceedings ArticleDOI
04 Mar 1999
TL;DR: An adaptive algorithm that can predict session lengths and shut down components between sessions to save power is proposed and simulations show that this algorithm can reduce power consumption in hard disks with less impact on performance or reliability.
Abstract: Dynamic power management can be effective for designing low-power systems. In many systems, requests are clustered into sessions. This paper proposes an adaptive algorithm that can predict session lengths and shut down components between sessions to save power. Compared to other approaches, simulations show that this algorithm can reduce power consumption in hard disks with less impact on performance or reliability.

103 citations