Thermal Modeling and Design Optimization of PCB Vias and Pads
Summary (4 min read)
A. Thermal Modeling of PCB Vias
- A cluster of PCB plated through holes (PTHs), i.e., vias, can provide an effective thermal path, which helps to transfer heat from an SMD (chip) to a heatsink.
- Also, the attached heatsink has a large heat dissipation capability.
- Accordingly, the PCB via array in each pattern can be divided into multiple via units, as indicated by the dashed box in Fig. 1 .
- The general equation for thermal conductivity is [32] / k q T , where q is the heat flux (W/m 2 ) and T represents the temperature gradient (K/m).
- The standard IPC-6012 specifies a minimum copper plating thickness of 20 µm for Class 1 PCBs, and 25 µm is a standard via plating thickness [37] .
1) Via-to-Via Spacing s
- Based on (5), the curves of the normalized via thermal resistance with respect to the via-to-via spacing s can be depicted for different filler materials, PCB thicknesses, and via diameters, as shown in Fig. 2 .
- It is seen that the normalized via thermal resistance via,n always rises when the via-to-via spacing s increases, regardless of the PCB thickness, via filling material and via diameter.
- Therefore, s should be designed as small as possible in order to reduce the thermal resistance of PCB via array.
- In practice, however, the allowed minimum via-to-via spacing depends on PCB manufacturing capability and is cost sensitive.
- Generally, 8 mil (0.2 mm) is a commonly-specified minimum via-to-via spacing by most PCB manufacturers, and therefore, s = 0.2 mm is used in the following analysis and experiments.
2) Number of layers NCu, PCB Thickness t, and Copper Layer Thickness tCu
- The dependence of the normalized thermal resistance of a PCB via array, via,n, on the number of copper layers NCu, copper thickness tCu, and PCB thickness t is shown in Fig. 3 .
- As can be seen, the parameters NCu, tCu and t, have a negligible impact on the normalized thermal resistance, implying that the copper and FR4 layers have a much higher thermal resistance compared to the vias.
- Thus the heat is mainly transferred through the vias, and (5) can be simplified as EQUATION ) ) ).
- Then, the dependence of the normalized thermal resistance on the via diameter and the filler material is illustrated in Fig. 4 (b) and (c).
- When the vias are not filled, the optimal via diameter is about 0.25 mm; if = 0.8 mm is chosen, then there will be a 44% increase in the thermal resistance.
C. Modeling of Outer-Zone Vias
- In some cases, the heatsink is larger than the chip, and thus the outer-zone vias can be added around the inner via array to further decrease the equivalent thermal resistance between the case and the heatsink, as shown in Fig. 5 .
- For the sake of simplicity, only via Pattern I is considered herein.
- The PCB vias can be divided into two zones, i.e., the inner-zone via array directly beneath the chip, and the outer-zone vias around the inner-zone via array, as illustrated in Fig. 5 (a) and (b).
1) Lumped Thermal Resistance Model
- Since there is a uniform heat source on the inner via array, and a powerful heatsink beneath the PCB, the radial-direction heat transfer of the inner-zone via array is not pronounced compared with the vertical direction.
- As for the outer-zone vias, the radial and vertical heat transfers are equally pronounced.
- Hence, both the distributed radial and vertical thermal resistances are taken into account, as shown in Fig. 5(a) .
- The cross transformation can be decoupled into a D-Y transformation and a Y-D transformation.
- Where i represents the copper layer order, and j denotes the outer via layer order.
2) Derivation of Equivalent Thermal Resistance
- The equivalent thermal resistance of the complicated network shown in Fig. 5(c ) can be derived by performing analog circuit simulations with given radial and vertical thermal resistance values as (8) .
- There are multiple design variables (e.g., , s, j) and system parameters (l, w, tCu, kfiller, tPTH, NCu, t), which implies that the method of circuit simulation does not support systematical parametric analysis.
- Therefore, a simple algorithm is developed in MATLAB to obtain the final equivalent thermal resistance of the complicated network (Fig. 5(c) ) with any values.
3) Parametric Analysis
- Based on the proposed thermal resistance model for outer-zone vias, the dependence of the ultimate thermal resistance of PCB vias on multiple design variables and parameter is plotted in Fig. 8 .
- If the maximum outer via layer number equals 0, then it means that there are only inner-zone vias.
- It is seen from Fig. 8 that the thermal resistance decreases with the increase of the outer via layer number.
- According to Fig. 8 (b), one can conclude that the filler material and via diameter affect the thermal resistance as well.
- In the case of air filling, the optimal diameter is 0.25 mm.
III. THERMAL MODELING AND SIZING OF PCB PADS
- For the natural convection in the air, the flow remains laminar when the temperature difference involved is less than 100 o C and the characteristic length of the body is less than 0.5 m [38] , which is almost always the case in electronic systems.
- When the PCB is composed of FR4 only (i.e., NCutCu = 0), its in-plane thermal conductivity reaches the minimum kFR4.
- Hence, the rectangular heat source and PCB pad are transformed to axisymmetric circular ones based on ensuring that the total area remains the same, as shown in Fig. 9(b ).
- As discussed in Section III-A, PCB pads can be regarded thin due to the negligible temperature drop over the vertical direction.
- Manipulating ( 21) and ( 23) yields the equivalent thermal resistance from rs to the ambient and the thermal resistance from re to the ambient when an axisymmetric heat source is located at rb.
D. Algorithm for Copper Pad Sizing
- When an SMD is mounted on a PCB, the heat generated inside the device will dissipate in two parallel pathways: one is from the junction, then to the top case, and finally to the ambient; the other is from the junction to the bottom case, then to the board, and finally to the ambient.
- Hence, the thermal resistances ta and ba are temperature dependent.
- Therefore, the initial iteration value of Tx,0 .
- A fixed-point iteration based algorithm taking into account all the five thermal resistances shown in Fig. 12 is developed to design the copper pad size, as shown in Fig. 14 .
- If all four temperatures errors are smaller than lmt, then the algorithm proceeds to calculate the junction temperature Tj according to (31) .
Give an initial temperature T e,g
- The average elapsed times are as short as approximately 30 ms.
- Personal use is permitted, but republication/redistribution requires IEEE permission.
- Selected initial iteration values, which agrees well with previous analysis.
- Nevertheless, the iteration can be further accelerated by using advanced methods, e.g., the Aitken's delta-squared process [47] and the Steffensen's method [48] . t = T t,c -T t,.
E. Thermal Modeling of DPAK Package
- Apart from the board to ambient thermal resistance ba, the realization of the proposed algorithm shown in Fig. 14 also requires the knowledge of the other four thermal resistances cb, jt, ta, and jc.
- Therefore, the detailed structure model and simplified package outline dimensions of DPAK package are derived, as shown in Fig. 16 .
- An analytical model of the thermal resistance ta is firstly developed.
- Its side and top surfaces are cooled by natural convection and radiation.
- Assume that the package is placed horizontally, and its surfaces share the same temperature Tt. For the horizontal top surfaces of the molding resin and die pad (see Fig. 16(b) ), their areas are Based on [38] , the characteristic lengths of the two rectangular surfaces under natural convection can be calculated as , respectively.
B. Experimental Verifications
- A curve tracer B1506A from Keysight Technologies is used to measure the I-V characteristics of a batch of VS-6EWL06FN-M3 diodes, as shown in Fig. 21 Each diode is soldered on a heatsink-cooled PCB with a specified via design.
- The maximum operating junction temperature of the selected diode VS-6EWL06FN-M3 is 175 o C [49] .
- In contrast, the existing model provides a minimum copper radius of 6.1 mm, which corresponds to an around 375% increase for the copper pad area compared to the design of re = 2.8 mm.
- To make a comparison, the results from the existing model and the proposed model (24) are shown in Fig. 25(c ) as well.
- Therefore, the proposed thermal models enable engineers to fast and easily optimize the design of PCB vias and thermal pads.
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"Thermal Modeling and Design Optimiz..." refers background or methods in this paper
...32 is a constant for horizontal plates [38]....
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...59 is a constant for vertical plates [38]....
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...The natural convection heat transfer coefficient for laminar flow of air at atmospheric pressure, hconv, and the radiation heat transfer coefficient hradi are [38] ⎧ ⎪⎪⎪⎨ ⎪⎪⎪⎩ hconv = λ[(Tx − Ta)/Lc] hradi = εσ[(Tx + 273) 2 + (Ta + 273) (2)] ×[(Tx + 273) + (Ta + 273)]...
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...5 m [38], which is almost always the case in electronic systems....
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...Then, we can obtain the convective heat transfer coefficients of the two top surfaces [38], i....
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...However, thermal management has been identified as the main barrier for further power density increase [4]....
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Frequently Asked Questions (13)
Q2. What is the effect of the parameters on the thermal resistance of a PCB via array?
3. As can be seen, the parameters NCu, tCu and t, have a negligible impact on the normalized thermal resistance, implying that the copper and FR4 layers have a much higher thermal resistance compared to the vias.
Q3. What is the thermal resistance of the inner-zone via array?
Since there is a uniform heat source on the inner via array, and a powerful heatsink beneath the PCB, the radialdirection heat transfer of the inner-zone via array is not pronounced compared with the vertical direction.
Q4. What is the maximum thermal resistance of a PCB via array?
4. When the vias are not filled, the optimal via diameter is about 0.25 mm; if = 0.8 mm is chosen, then there will be a 44% increase in the thermal resistance.
Q5. What is the thermal resistance of the network shown in Fig. 5(c)?
it is observed from (8) that both the radial and vertical outer-zone thermal resistances are functions of j, implying the two types of thermal resistances vary with respect to the outer via layer number.
Q6. Why is the thermal resistance in the cylindrical coordinates easier to analyze?
Due to the phenomena of radial heat conduction and vertical heat convection in the PCB thermal system shown in Fig. 9(a), it is much easier to analyze the thermal resistance in the cylindrical coordinates.
Q7. How is the temperature of the PCB cooled?
When the steady state of the thermal system is reached, the temperature does notchange with time , and thus, (14) can be simplified as22d 1 d 0 dd T T P r r kr (15)The PCB is cooled by means of natural convection andradiation.
Q8. What is the simplest method to design the copper pad size?
A fixed-point iteration based algorithm taking into account all the five thermal resistances shown in Fig. 12 is developed to design the copper pad size, as shown in Fig. 14.
Q9. What is the thermal resistance of a PCB via array?
When the vias are filled up with high-thermal-conductivity solder, then the via array with = 0.8 mm has the minimum thermal resistance.
Q10. What is the equivalent thermal resistance of Fig. 5(c)?
a simplification method consisting of various steps of network transformations is proposed to derive the equivalent thermal resistance of Fig. 5(c), as illustrated in Fig.
Q11. What is the thermal resistance of the via array?
With the same area for the via array, the thermal resistanceof Pattern II is about √3/2 = 86.6% of that in Pattern I. From (6), the authors can also obtain the optimal via diameter for both patterns, which can achieve the minimum thermal resistance, i.e.,2 ( 2 )( ) , Patterns The author& II2 ( ) PTH PTH
Q12. What is the thermal resistance of PCB pads?
The existing analytical thermal resistance model for PCB pads overestimates the junction temperatures ofSMDs, whereas the proposed model enables a more accurate junction temperature prediction.
Q13. How much thermal resistance can be reduced with the proposed design?
Compared to the reference design provided in [15], the thermal resistance can be reduced up to 62%, i.e., from 2.63 K/W (seeFig. 18(a)) based on [15] to 0.98 K/W with the proposed optimal design trajectory (Pattern II, = 0.8 mm, solder filling, see Fig. 18(b)).