Journal ArticleDOI
Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias
Toshiaki Kirihata,John Golz,Matthew R. Wordeman,Pooja R. Batra,Gary W. Maier,Norman Robson,Troy L. Graves-Abe,Daniel Berger,Subramanian S. Iyer +8 more
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TLDR
3D DRAMs including DDR3, wide I/O mobile DRAM, and more recently, the hybrid-memory cube (HMC) and high-bandwidth memory (HBM) targeted for high-performance computing systems are reviewed.Abstract:
This paper describes orthogonal scaling of dynamic-random-access-memories (DRAMs) using through-silicon-vias (TSVs). We review 3D DRAMs including DDR3, wide I/O mobile DRAM (WIDE I/O), and more recently, the hybrid-memory cube (HMC) and high-bandwidth memory (HBM) targeted for high-performance computing systems. We then cover embedded 3D DRAM for high-performance cache memories, reviewing an early cache prototype employing face-to-face 3D stacking which confirmed negligible performance and retention degradation using 32 nm server and ASIC embedded DRAM macros. A second cache system prototype based on POWER7 was developed to confirm feasibility of stacking $\mu {\rm P}$ and high density cache memory, with $> 2~{\rm GHz}$ operation. For test and assembly, a micro-electro-mechanical-system (MEMS) probe-card with an integrated active silicon chip, realized a 50 $\mu{\rm m}$ pitch micro-probing at-speed-active-test for known-good-die (KGD) sorting. Finally, oxide wafer bonding with Cu TSV demonstrated wafer-scale 3D integration, with TSV diameters as small as 1 $\mu{\rm m}$ . The paper concludes with comments on the challenges for future 3D DRAMs.read more
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Journal ArticleDOI
Micro/Nanoscale 3D Assembly by Rolling, Folding, Curving, and Buckling Approaches.
Xu Cheng,Yihui Zhang +1 more
TL;DR: The latest progress in the area of micro/nanoscale 3D assembly, covering the various classes of methods through rolling, folding, curving, and buckling assembly, is discussed, focusing on the design concepts, principles, and applications of different methods, followed by an outlook on the remaining challenges and open opportunities.
Journal ArticleDOI
Intermetallic compounds in 3D integrated circuits technology: a brief review.
TL;DR: Technologies related to 3D-ICs, IMCs formation mechanisms and reliability issues concerning IMCs with Pb-free solder microbumps are reviewed and future outlook on the potential growth of research in this area is discussed.
Journal ArticleDOI
Manufacturing of 3D multifunctional microelectronic devices: challenges and opportunities
TL;DR: In this paper, the authors present a review of different manufacturing methods and their specific features as well as their limitations for 3D multifunctional microelectronic devices and offer an outlook on future developments in the manufacturing of 3D multi-functional microelectronics devices and provide some perspectives on the remaining challenges.
Journal ArticleDOI
A $4 \times 4 \times 2$ Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links
Pascal Vivet,Yvain Thonnart,Romain Lemaire,Cristiano Santos,Edith Beigne,Christian Bernard,Florian Darve,Didier Lattard,Ivan Miro-Panades,Denis Dutoit,Fabien Clermidy,S. Cheramy,Abbas Sheibanyrad,Frédéric Pétrot,Eric Flamand,Jean Michailos,Alexandre Arriordaz,Lee Wang,Juergen Schloeffel +18 more
TL;DR: A 3D modular and scalable network-on-chip (NoC) architecture implemented using robust asynchronous logic and the scalability of the 3DNOC circuit, in terms of power delivery network and thermal dissipation, is demonstrated by using simulations up to a 3D stack of eight die layers.
Journal ArticleDOI
Architecture of Computing System based on Chiplet
TL;DR: This paper reviews the Chiplet-based computing system architectures, including computing architecture and memory architecture, and introduces the memory architecture based on mainstream memory and emerging non-volatile memory used for data storing and processing.
References
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Proceedings ArticleDOI
Hybrid memory cube new DRAM architecture increases density and performance
Joe M. Jeddeloh,Brent Keeth +1 more
TL;DR: The Hybrid Memory Cube is a three-dimensional DRAM architecture that improves latency, bandwidth, power and density and Heterogeneous die are stacked with significantly more connections, thereby reducing the distance signals travel.
Proceedings ArticleDOI
Use ECP, not ECC, for hard failures in resistive memories
TL;DR: Error-Correcting Pointers (ECP), a new approach to error correction optimized for memories in which errors are the result of permanent cell failures that occur, and are immediately detectable, at write time, provides longer lifetimes than previously proposed solutions with equivalent overhead.
Journal ArticleDOI
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 $\times$ 128 I/Os Using TSV Based Stacking
Jung-Sik Kim,Chi Sung Oh,Ho-Cheol Lee,Donghyuk Lee,Hyong-Ryol Hwang,Sooman Hwang,Byongwook Na,Joung-Wook Moon,Jin-Guk Kim,Hanna Park,Jang-Woo Ryu,Ki-Won Park,Sang-Kyu Kang,So-Young Kim,Ho-Young Kim,Jong-Min Bang,Hyunyoon Cho,Min-Soo Jang,Cheolmin Han,Jung-Bae Lee,Kye-Hyun Kyung,Joo-Sun Choi,Young-Hyun Jun +22 more
TL;DR: A 1.2 V 1 Gb mobile SDRAM, having 4 channels with 512 DQ pins has been developed with 50 nm technology, exhibiting 330.6 mW read operating power during 4 channel operation, achieving 12.8 GB/s data bandwidth.