Three dimensional modeling of SOI four gate transistors
03 Dec 2010-pp 383-388
TL;DR: In this article, a mathematical model is developed to determine the 3D potential distribution of a fully-depleted silicon-on-insulator (SOI) four-gate transistor (G4-FET).
Abstract: A mathematical model is developed to determine the 3-D potential distribution of a fully-depleted silicon-on-insulator (SOI) four-gate transistor (G4-FET). The potential distributions along the channel and between the junction-gates are assumed to be parabolic due to short channel effect. Using these two assumptions, the 3-D potential distribution model is developed. From the 3-D model, expression for threshold voltage is derived considering all possible charge conditions at the back surface. The proposed models successfully correlate the effect of all four gates and consider the impact of channel length, drain voltage and other device dimensions.
Citations
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28 May 2019
TL;DR: This chapter shows how different modeling approaches can be used to simulate three emerging semiconductor devices namely, silicononinsulator four gate transistor(GFET), perimeter gated single photon avalanche diode (PG-SPAD) and insulator-metal transistor (IMT) device with volatile memristance.
Abstract: Circuit simulation is an indispensable part of modern IC design. The significant cost of fabrication has driven researchers to verify the chip functionality through simulation before submitting the design for final fabrication. With the impending end of Moore’s Law, researchers all over the world are looking for new devices with enhanced functionality. A plethora of promising emerging devices has been proposed in recent years. In order to leverage the full potential of such devices, circuit designers need fast, reliable models for SPICE simulation to explore different applications. Most of these new devices have complex underlying physical mechanism rendering the model development an extremely challenging task. For the models to be of practical use, they have to enable fast and accurate simulation that rules out the possibility of numerically solving a system of partial differential equations to arrive at a solution. In this chapter, we show how different modeling approaches can be used to simulate three emerging semiconductor devices namely, silicononinsulator four gate transistor(GFET), perimeter gated single photon avalanche diode (PG-SPAD) and insulator-metal transistor (IMT) device with volatile memristance. All the models have been verified against experimental /TCAD data and implemented in commercial circuit simulator.
5 citations
15 Mar 2012
TL;DR: In this article, the structure of a SOI four-gate transistor (G4-FET) and its different parameters for different biasing conditions are studied. And a simulation model was developed by Silvaco/Atlas 3-D simulator which incorporates non-ideal effects like concentration dependent mobility, Shockley-Read-Hall recombination, Auger recombinations, bandgap narrowing effect.
Abstract: The structure of silicon-on-insulator (SOI) four-gate transistor (G4-FET) and its different parameters for different biasing conditions are studied. A G4-FET simulation model was developed by Silvaco/Atlas 3-D simulator which incorporates non-ideal effects like concentration dependent mobility, Shockley-Read-Hall recombination, Auger recombination, bandgap narrowing effect. This model can be useful in measuring parameters dependency of a SOI four gate transistor.
4 citations
Cites background or methods from "Three dimensional modeling of SOI f..."
...The simulation work of the developed 3-D G4-FET model verifies the 2-D analytical model [2] and 3-D analytical approach in [1], [6]....
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...7(a) to clarify the operation and proposition of analytical model [1], [6]....
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...Earlier works on G4-FET reported an analytical modeling of 2-D potential distribution [2] and extended to 3-D potential distribution [1] considering the effect of the length of the device and also the drain voltage....
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...In this work, an Atlas/Silvaco 3-D model is developed to validate the results of the analytical modeling of 3-D potential distribution presented in [1] and the effect of variation of different parameters like length, width, thickness, biasing and operation mode of a fully depleted SOl G4-FET is completely studied....
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01 Dec 2012
TL;DR: A comparative study of two different analytical models of accumulationmode SOI p-channel G4-FET has been reported and accuracy of the models has been observed under different parametric variation and biasing conditions.
Abstract: A comparative study of two different analytical models of accumulation-mode SOI p-channel G4-FET has been reported and accuracy of the models has been observed under different parametric variation and biasing conditions A numerical model is developed by Silvaco/ATLAS 3-D simulator which incorporates various non ideal effects like concentration dependant mobility, Shockley-Read-Hall recombination, Auger recombination and bandgap narrowing effect The accuracy of the analytical models are tested by the numerical model The performance of varying different parameters like length, width, silicon thickness and gate biasing is also observed between lateral junction gates and between top and bottom gates
3 citations
01 Jan 2017
2 citations
Cites background from "Three dimensional modeling of SOI f..."
...Another mathematical model is developed in [32] to determine the 3-D potential distribution of a fully-depleted G(4)FET....
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01 Dec 2012
TL;DR: In this article, a surface potential based analytical model is used for studying threshold voltage and an Atlas/Silvaco 3-D numerical model is also developed for the validation of the analytical model.
Abstract: Threshold voltage of a SOI four gate transistor is studied to determine its dependency on different device parameters. A surface potential based analytical model is used for studying threshold voltage and an Atlas/Silvaco 3-D numerical model is also developed for the validation of the analytical model. The numerical model incorporates non-ideal effects like Shockley-Read-Hall recombination, concentration dependent mobility, Auger recombination and bandgap narrowing effect. Threshold voltage sensitivity on channel length variation is reduced by controlling device width (W) and silicon layer thickness (tsi). The idea is justified by both analytical model and numerical model.
2 citations
References
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TL;DR: In this article, the short channel effect in fully depleted silicon-on-insulator MOSFETs has been studied by a two-dimensional analytical model and by computer simulation, and it is found that the vertical field through the depleted film strongly influences the lateral field across the source and drain regions.
Abstract: The short-channel effect in fully depleted silicon-on-insulator MOSFETs has been studied by a two-dimensional analytical model and by computer simulation. The calculated values agree well with the simulation results. It is found that the vertical field through the depleted film strongly influences the lateral field across the source and drain regions. The short-channel effect can be significantly reduced by decreasing the silicon film thickness. >
789 citations
"Three dimensional modeling of SOI f..." refers background in this paper
...This assumption is usually made in dealing with short channel effects [5]....
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TL;DR: In this article, the charge coupling between the front and back gates of thin-film silicon-on-insulator (SOI) MOSFETs is analyzed, and closed-form expressions for the threshold voltage under all possible steady-state conditions are derived.
Abstract: The charge coupling between the front and back gates of thin-film silicon-on-insulator (SOI: e.g,, recrystallized Si on SiO 2 ) MOSFET's is analyzed, and closed-form expressions for the threshold voltage under all possible steady-state conditions are derived. The expressions clearly show the dependence of the linear-region channel conductance on the back-gate bias and on the device parameters, including those of the back silicon-insulator interface. The analysis is supported by current-voltage measurements of laser-recrystallized SOI MOSFET's. The results suggest how the back-gate bias may be used to optimize the performance of the SOI MOSFET in particular applications.
662 citations
"Three dimensional modeling of SOI f..." refers background in this paper
...In strong accumulation or inversion, the surface potential increases beyond the classical values (ψs2 = 0 and ψs2 = VJG + 2φF ) by a few thermal voltages Vt [8]....
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TL;DR: In this article, a model developed to explain conduction mechanisms in thin-film accumulation-mode SOI p-channel MOSFETs is discussed, and the model is used to calculate drain current as a function of front and back-gate bias as well as output characteristics.
Abstract: A model developed to explain conduction mechanisms in thin-film accumulation-mode SOI p-channel MOSFETs is discussed. It is found that, unlike that which occurs in thin-film fully depleted n-channel devices, there is little or no coupling between the front and back gates, unless the surface-state density is so high that the film remains depleted even when an accumulation channel is formed. The apparent front threshold shift is explained by back-gate modulation of a body current, flowing from the source to the drain. Indeed, the body of the device presents a p/sup +/-p/sup -/-p/sup +/ structure whose conductivity is controlled by the depth of the depletion zones arising from the top and the bottom of the silicon film. The model is used to calculate drain current as a function of front- and back-gate bias as well as output characteristics. >
137 citations
"Three dimensional modeling of SOI f..." refers background in this paper
...MODELING OF FRONT-GATE THRESHOLD VOLTAGE When the channel is partially-depleted, front-gate threshold voltage is simply equal to the flat-band voltage [7]....
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TL;DR: In this paper, low-frequency noise characteristics of the silicon-on-insulator four-gate transistor [G/sup 4/-field effect transistor] are reported and the noise power spectral density as a function of biasing conditions is compared for surface and volume conduction modes.
Abstract: Low-frequency noise characteristics of the silicon-on-insulator four-gate transistor [G/sup 4/-field-effect transistor] are reported. The noise power spectral density as a function of biasing conditions is presented and compared for surface and volume conduction modes. It is shown that, for the same drain current, the volume of the transistor generates less noise than its surface. The possible transition from carrier-number fluctuations to mobility fluctuations as the conducting channel is moved away from the surface toward the volume is also discussed.
51 citations
"Three dimensional modeling of SOI f..." refers background or result in this paper
...Lateral Position (nm) Proposed model Result in [6]...
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...Result of (27) is compared with the result in [6] which is shown in Fig....
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TL;DR: In this paper, the 2D analytical body potential is derived by assuming a parabolic potential variation between the lateral junction-gates and by solving Poisson's equation, which is used to obtain the surface threshold voltage of the G4-FET as a function of the lateral gate bias and for all possible charge conditions at the back interface.
Abstract: The two-dimensional (2-D) channel potential and threshold voltage of the silicon-on-insulator (SOI) four-gate transistor (G4-FET) are modeled. The 2-D analytical body potential is derived by assuming a parabolic potential variation between the lateral junction-gates and by solving Poisson's equation. The model is used to obtain the surface threshold voltage of the G4-FET as a function of the lateral gate bias and for all possible charge conditions at the back interface. The body-potential model is extendable to fully depleted SOI MOSFETs and can serve to depict the charge-sharing and drain-induced barrier-lowering effects in short-channel devices
49 citations