Three-Layer Channel Routing
01 Apr 1984-IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE)-Vol. 3, Iss: 2, pp 156-163
TL;DR: Two special types of three-layer channel routing, VHV and HVH, are introduced in this paper, and the merging algorithm and the left edge algorithm used in two-layer routing can be extended to three layers.
Abstract: With the advent of VLSI technology, multiple-layer routing becomes feasible. Two special types of three-layer channel routing, VHV and HVH, are introduced in this paper. The merging algorithm and the left edge algorithm used in two-layer routing can be extended to three layers. Attempts are made to compare the lower bounds of channel width of three types of routing--two-layer, VHV, and HVH. The algorithms were coded in PASCAL and implemented on VAX 11/780 computer. The computational results are satisfactory, since all the results lead to a further reduction in routing area.
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Book•
31 Jan 1993
TL;DR: This book is a core reference for graduate students and CAD professionals and presents a balance of theory and practice in a intuitive manner.
Abstract: From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.
927 citations
01 Feb 1990
TL;DR: The current status of VLSI layout and directions for future research are addressed, and the field of computational geometry and its application to layout-in particular, to gridless routing and compaction-are reviewed, and layout engines are considered.
Abstract: The current status of VLSI layout and directions for future research are addressed, with emphasis on the authors' own work Necessary terminology and definitions and, whenever possible, a precise formulation of the problems are provided Placement and floorplanning for both the sea-of-gates and building-block designs are examined The former emphasizes the connectivity specification, whereas the latter must also consider module shape and size Global routing based on a method of successive cuts on a chip is discussed This is a hierarchical top-down approach that is useful for both of the above designs A two-dimensional detailed routing problem and the rip-up and rerouting problem are also discussed The field of computational geometry and its application to layout-in particular, to gridless routing and compaction-are reviewed, and layout engines are considered >
225 citations
02 Jul 1986
TL;DR: Two n -layer channel routing algorithms that guarantee successful routing of the channel for n greater than three are presented and one is linear and optimal given a VHV …HV assignment of layers and the other is quasilinear and performs optimally on examples from the literature.
Abstract: In this paper we present two n-layer channel routing algorithms that guarantee successful routing of the channel for n greater than three. The first is linear and optimal given a VHV...HV assignment of layers. The second, using an HVH...VH layer assignment, is quasilinear and performs optimally on examples from the literature. Except in pathological cases, we expect the latter router to perform within one row of optimal. For comparison with published examples we implemented the second router in five and three layers. The five-layer implementation routed all examples optimally while the three-layer implementation routed the examples with the same or fewer rows than the published examples. With its n-layer capability this channel router will allow channel routing to be used when more than three layers are available. This router can also be used to evaluate the utility of additional layers.
103 citations
Proceedings Article•
01 Jan 1986
TL;DR: A new routing technique that can be applied for general two-layer detailed routing problems including switch boxes, channels and partially routed areas, is presented and has performed as well or better than existing algorithms.
Abstract: For the macro-cell design style and for routing problems where the routing regions are irregular, two dimensional routers are often necessary. In this paper a new routing technique that can be applied for general two-layer detailed routing problems including switch boxes, channels and partially routed areas, is presented. The routing regions that can be handled are very general: the boundaries can be described by any rectilinear chains and the pins can be on the boundaries of the region or inside it, the obstructions can be of any shape and size. The technique is based on an algorithm that routes incrementally and intelligently the nets in the routing region and allows modifications and rip-up of nets that may impede the complete routing of other nets. The modification steps (also called weak modification) push some segments of nets already routed to make room for a blocked net. The rip-up and re-route steps (called strong modification), remove segments of nets already routed to make room for a blocked connection and is invoked only if weak modification fails. The algorithm is rigorously proven to complete in finite time and its complexity is analyzed. Many test cases have been run and on all the examples known in the literature the router has performed as well or better than existing algorithms. In particular, the Burstein's difficult switch box example has been routed using one less column than the original data. In addition, the router has routed difficult channels such as Deutsch's in density and has performed better than or as well as YACR-II in all the channels available to us. REFERENCES
70 citations
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References
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TL;DR: Two new algorithms merge nets instead of assigning horizontal tracks to individual nets to route a specified net list between two rows of terminals across a two-layer channel in the layout design of LSI chips.
Abstract: In the layout design of LSI chips, channel routing is one of the key problems. The problem is to route a specified net list between two rows of terminals across a two-layer channel. Nets are routed with horizontal segments on one layer and vertical segments on the other. Connections between two layers are made through via holes. Two new algorithms are proposed. These algorithms merge nets instead of assigning horizontal tracks to individual nets. The algorithms were coded in Fortran and implemented on a VAX 11/780 computer. Experimental results are quite encouraging. Both programs generated optimal solutions in 6 out of 8 cases, using examples in previously published papers. The computation times of the algorithms for a typical channel (300 terminals, 70 nets) are 1.0 and 2.1 s, respectively.
539 citations
28 Jun 1976
TL;DR: The routing algorithm presented here was developed as part of LTX, a computer-aided design system for integrated circuit layout and was implemented on an HP-2100 minicomputer.
Abstract: This paper presents an algorithm for interconnecting two sets of terminals across an intervening channel. It is assumed that the routing is done on two distinct levels with all horizontal paths being assigned to one level and all vertical paths to the other. Connections between the levels are made through contact windows. A single net may result in many horizontal and vertical segments. Experimental results indicate that this algorithm is very successful in routing channels that contain severe constraints. Usually, the routing is accomplished within one track of the mathematical lower bound. The routing algorithm presented here was developed as part of LTX, a computer-aided design system for integrated circuit layout and was implemented on an HP-2100 minicomputer. A typical channel (300 terminals, 100 nets) can be routed in less than 5 seconds. Routing results are presented both for polycell chips under development at Bell Laboratories and for examples that exist in the published literature. For the latter, reductions of 10% in the wiring area were typical.
364 citations
[...]
TL;DR: A general overview of circuit layout, taking a unified approach to various styles of integrated circuits, printed circuit boards, and hybrid circuits, and problems associated with the implementation of a hierarchical system are discussed.
Abstract: This paper gives a general overview of circuit layout, taking a unified approach to various styles of integrated circuits, printed circuit boards, and hybrid circuits. A lot of attention is given to the layout of large and complicated circuits, in particular, to the layout of very-large-scale-integration (VLSI) chips. Though the paper is an overview, and one could almost say a tutorial, it is intended for readers with some basic knowledge of what a circuit layout is and what some of the basic problems are. The main subjects discussed are: assignment of gates, placement methods, loose routing, final routing, and problems associated with the implementation of a hierarchical system. The emphasis is on new, not widely published methods, and on methods that seem to have potential for solving some of the current problems. Practical examples illustrate this rather personal account of circuit layout and sugsest where we may go from here.
211 citations
28 Jun 1976
TL;DR: LTX is a minicomputer-based design system for large-scale integrated circuit chip layout which offers a flexible set of interactive and automatic procedures for translating a circuit connectivity description into a finished mask design.
Abstract: LTX is a minicomputer-based design system for large-scale integrated circuit chip layout which offers a flexible set of interactive and automatic procedures for translating a circuit connectivity description into a finished mask design. The system encompasses algorithms for two-dimensional placement, string placement, exploitation of equivalent terminals, decomposition of routing into channels, and channel routing. Circuit connectivity is preserved during interactive procedures. LTX runs on an H-P 2100 series computer with 32K of memory and disc.In current applications to polycell-style layouts, one to two weeks is typically required for completion of the layout design of an LSI chip containing 500 cells.
71 citations