Threshold voltage modeling of Deeply Depleted Channel MOSFET and simulation study of its analog performances
17 Mar 2014-pp 1-4
TL;DR: In this paper, the analytical models for the long channel and short channel threshold voltage of Deeply Depleted Channel (DDC) MOS transistor were presented and compared with TCAD simulation results.
Abstract: This paper presents the analytical models for the long channel and short channel threshold voltage of Deeply Depleted Channel (DDC) MOS transistor. The model predicted results are compared with TCAD simulation results. This paper also reports the comparative study of the analog performances of the DDC MOS transistor with those of a uniformly doped transistor. The TCAD tool is calibrated with published data of DDC MOS transistor. The better immunity of the DDC MOS transistor in comparison to the conventional bulk MOS transistor is demonstrated through simulation results.
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Book•
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IBM1
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Abstract: Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.
2,655 citations
"Threshold voltage modeling of Deepl..." refers background in this paper
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Patent•
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TL;DR: In this paper, the Deeply Depleted Channel (DDC) transistors are used to reduce power consumption in devices by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as broader electronics industry to avoid a costly and risky switch to alternative technologies.
Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
193 citations
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TL;DR: A methodology to verify the robustness of the test structures is described and a set of grid specifications was generated for simulation accuracy and computational efficiency of a device simulation program.
Abstract: This paper describes a quantitative methodology for the selection of simulation space and the generation of MOSFET mesh for two-dimensional device simulation Simple mathematical expressions for the selection of two-dimensional device geometries are presented A set of grid specifications was generated for simulation accuracy and computational efficiency of a device simulation program These grid specifications were used in conjunction with the grid generation algorithm in the device simulation program MEDICI to generate two-dimensional nMOSFET test structures of different channel lengths A methodology to verify the robustness of the test structures is also described
80 citations
"Threshold voltage modeling of Deepl..." refers methods in this paper
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TL;DR: The DDC transistor has been successfully integrated into an existing 65nm CMOS platform by combining layered channel formation and low temperature processing.
Abstract: We have achieved aggressive reduction of V T variation and V DD-min by a sophisticated planar bulk MOSFET named ‘Deeply Depleted Channel ™ (DDC)’. The DDC transistor has been successfully integrated into an existing 65nm CMOS platform by combining layered channel formation and low temperature processing. The 2x reduction of V T variation in 65nm-node has been demonstrated by matching SRAM pair transistors, 2x improvement in SRAM static noise margin (SNM) and 300 mV V DD-min reduction of 576Kb SRAM macros to 0.425 V using conventional 6T cell layout.
71 citations
"Threshold voltage modeling of Deepl..." refers methods in this paper
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TL;DR: In this article, a simple analytical model for the lateral channel electric field in the drain region of MOSFET's with graded-drain or lightly doped drain structures is presented.
Abstract: A simple analytical model for the lateral channel electric field in the drain region of MOSFET's with graded-drain or lightly doped drain structures is presented. The model's results agree well with two-dimensional simulations of the electric field in the drain region. Due to its simplicity, this model gives a better understanding of the mechanisms involved in reducing the electric field in the lightly doped region. Results show the impact of the length and doping concentration, assumed to be Gaussian, of the lightly doped region on the electric field. Effects of the oxide thickness and junction depth are also accounted for. In each case, there is an optimum doping concentration that minimizes the peak electric field.
64 citations
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