Trapping characteristics of Al2O3/HfO2/SiO2 stack structure prepared by low temperature in situ oxidation in dc sputtering
TL;DR: In this paper, a dielectric stack with Al2O3/HfO2/SiO2 (18 nm/16 nm/25 nm) trilayer structure prepared by low temperature in situ natural oxidation during dc sputtering is investigated.
Abstract: In this work, a dielectric stack with Al2O3/HfO2/SiO2 (18 nm/16 nm/25 nm) trilayer structure prepared by low temperature in situ natural oxidation during dc sputtering is investigated We study the electrical characteristics, including the dielectric leakage of 10−8 A/cm2 at Vg=−2 V, the current transport mechanism and trap distributions through the trilayer dielectric stack The Fowler–Nordheim barrier height of the prepared Al2O3 (ϕFN,Al2O3) was extracted as 306±015 eV The current variation ratios [ΔJg/Jg(0)] during constant voltage stressing were found to decrease with raising gate stress voltages for the trilayer stack in comparison with that [ΔJg/Jg(0)] increase with raising gate stress voltages for the two-layer HfO2/SiO2 stack Shallow traps located in HfO2 were supposed to be major trapping centers within the trilayer stack The proposed method of in situ oxidation during dc sputtering is of merit and low in process temperature The trilayer dielectric stacks are an alternative option for no
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TL;DR: In this article, the authors studied the deep depletion behaviors at the structure of Si/SiO2 with various equivalent oxide thicknesses (EOTs) and comprehensively studied by magnified capacitance versus gate voltage (C-V) curves of metal-oxide-semiconductor (P-substrate) capacitors.
Abstract: The deep depletion behaviors at the structure of Si/SiO2 with various equivalent oxide thicknesses (EOTs) are comprehensively studied by magnified capacitance versus gate voltage (C-V) curves of metal-oxide-semiconductor (P-substrate) capacitors in this work. According to the correlation between inversion tunneling current and deep depletion, it was found that the initiation voltage of deep depletion phenomenon increases with EOT (2.8–3.1 nm). After the constant voltage stress, the early occurrence of initiation voltage of deep depletion is observed after oxide breakdown. In addition, the uniform area ratio concept is proposed for the electrical characterization of deep depletion via local depletion capacitance model. It was novel for the evaluation of interfacial property between dielectric and Si substrate.
30 citations
TL;DR: In this paper, the temperature dependence of C-V and I-V characteristics in p-type MOS capacitors with HfO2/SiO2 dielectric stacks was investigated, which was caused by increased effective oxide thickness, oxide trapped charge density, and interfacial density of state with rising temperature during bias temperature stress.
Abstract: We investigated the temperature dependence of C–V and I–V characteristics in p-type Metal Oxide Semiconductor (MOS) capacitors with HfO2/SiO2 dielectric stacks Dramatic degradation in the C–V characteristics at/over the measurement temperature of 125 °C was observed, which was caused by the increased effective oxide thickness, oxide trapped charge density, and interfacial density of state (Dit) with rising temperature during bias temperature stress In the accumulation region, the leakage current density displayed strong temperature dependence in the −3 V
27 citations
01 Jan 2013-Journal of Vacuum Science & Technology. B. Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena
TL;DR: In this paper, the effects of the oxidant source (H2O or O3) and postdeposition anneal on the charging phenomena and the generation of new defects during electrical stress were investigated.
Abstract: In this work, the authors focus on the charge trapping behavior of Al2O3 layers deposited by atomic layer deposition. The goal is to give an insight into the effects of the oxidant source (H2O or O3) and the postdeposition anneal on the charging phenomena and the generation of new defects during electrical stress. For this purpose, current–voltage, capacitance–voltage, and conductance–voltage characteristics of Al/Al2O3/p-Si capacitors are analyzed before and after constant voltage stress and several phenomena such as the generation of neutral traps in the bulk dielectric, slow states, interface states, and charge trapping related degradation during the electrical stress are investigated. Finally, the impact of the oxidant source on the Al2O3 layer reliability is discussed.
25 citations
TL;DR: In this article, a metal-oxide-semiconductor (MOS) photodetector with the high-k material enhanced deep depletion at edge was demonstrated, where the mechanism of saturated substrate injection current in MOS capacitor was adopted.
Abstract: Metal-oxide-semiconductor (MOS) photodetector with the high-k material enhanced deep depletion at edge was demonstrated. The mechanism of saturated substrate injection current in MOS capacitor was adopted. By building HfO2 based devices that with the direct observation of the enhanced edge charge collection efficiency due to fringing field effect in inversion, we are able to show a photodetector with 3000 times (ratio of photocurrent to dark current) improvement in sensitivity than the conventional SiO2 based tunneling photodiodes (approximate 100 times) in the visible.
21 citations
TL;DR: In this paper, the authors investigated the charge-trapping characteristics of BaTiO3 film with and without Zr incorporation based on Al/ Al2O3/BaTiO 3/SiO2/Si capacitors.
Abstract: The charge-trapping characteristics of BaTiO3 film with and without Zr incorporation were investigated based on Al/ Al2O3/BaTiO3/SiO2/Si capacitors. Compared with the device without Zr incorporation, the one with Zr incorporation showed a similar memory window (8.3 V at ±12 V for 1 s), but higher program speed at low gate voltage (3.2 V at 100 μs + 6 V) and better endurance and data retention (charge loss of 6.4% at 150°C for 104), due to the Zr-doped BaTiO3 exhibiting higher charge-trapping efficiency and higher density of traps with deeper energy levels.
20 citations
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...The barrier height ΦB of the Al/CTL interface is extracted from the slope of the fitted line [12]....
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14,205 citations
TL;DR: In this paper, the Schottky barrier heights and band offsets for high dielectric constant oxides on Pt and Si were calculated and good agreement with experiment is found for barrier heights.
Abstract: Wide-band-gap oxides such as SrTiO3 are shown to be critical tests of theories of Schottky barrier heights based on metal-induced gap states and charge neutrality levels. This theory is reviewed and used to calculate the Schottky barrier heights and band offsets for many important high dielectric constant oxides on Pt and Si. Good agreement with experiment is found for barrier heights. The band offsets for electrons on Si are found to be small for many key oxides such as SrTiO3 and Ta2O5 which limit their utility as gate oxides in future silicon field effect transistors. The calculations are extended to screen other proposed oxides such as BaZrO3. ZrO2, HfO2, La2O3, Y2O3, HfSiO4, and ZrSiO4. Predictions are also given for barrier heights of the ferroelectric oxides Pb1−xZrxTiO3 and SrBi2Ta2O9 which are used in nonvolatile memories.
1,947 citations
TL;DR: In this article, a gate dielectric film with metal contents ranging from ∼3 to 30 at. % Hf and Zr has been investigated, and the results show that Hf exhibits excellent electrical properties and high thermal stability in direct contact with Si, while Al electrodes produce very good electrical properties, but also react with the silicates.
Abstract: Hafnium and zirconium silicate (HfSixOy and ZrSixOy, respectively) gate dielectric films with metal contents ranging from ∼3 to 30 at. % Hf, or 2 to 27 at. % Zr (±1 at. % for Hf and Zr, respectively, within a given film), have been investigated, and films with ∼2–8 at. % Hf or Zr exhibit excellent electrical properties and high thermal stability in direct contact with Si. Capacitance–voltage measurements show an equivalent oxide thickness tox of about 18 A (21 A) for a 50 A HfSixOy (50 A ZrSixOy) film deposited directly on a Si substrate. Current–voltage measurements show for the same films a leakage current of less than 2×10−6 A/cm2 at 1.0 V bias. Hysteresis in these films is measured to be less than 10 mV, the breakdown field is measured to be EBD∼10 MV/cm, and the midgap interface state density is estimated to be Dit∼1–5×1011 cm−2 eV−1. Au electrodes produce excellent electrical properties, while Al electrodes produce very good electrical results, but also react with the silicates, creating a lower e l...
1,001 citations
TL;DR: The results indicate that the hybrid organic/inorganic memory device is a reliable means for achieving rapid, large-scale archival data storage for ultralow-cost permanent storage of digital images, eliminating the need for slow, bulky and expensive mechanical drives used in conventional magnetic and optical memories.
Abstract: Organic devices promise to revolutionize the extent of, and access to, electronics by providing extremely inexpensive, lightweight and capable ubiquitous components that are printed onto plastic, glass or metal foils1,2,3. One key component of an electronic circuit that has thus far received surprisingly little attention is an organic electronic memory. Here we report an architecture for a write-once read-many-times (WORM) memory, based on the hybrid integration of an electrochromic polymer with a thin-film silicon diode deposited onto a flexible metal foil substrate. WORM memories are desirable for ultralow-cost permanent storage of digital images, eliminating the need for slow, bulky and expensive mechanical drives used in conventional magnetic and optical memories. Our results indicate that the hybrid organic/inorganic memory device is a reliable means for achieving rapid, large-scale archival data storage. The WORM memory pixel exploits a mechanism of current-controlled, thermally activated un-doping of a two-component electrochromic conducting polymer.
731 citations