Trends in memory technology - reliability perspectives, challenges and opportunities
11 Jul 2007-pp 130-134
TL;DR: As DRAM and NAND cells are rapidly scaled deep into the nanoscale regime, meeting design and reliability requirements require deeper understanding of single-cell characteristics.
Abstract: As DRAM and NAND cells are rapidly scaled deep into the nanoscale regime, meeting design and reliability requirements require deeper understanding of single-cell characteristics. Some of the challenges are common between these technologies while some are unique. New materials and cell structures are being introduced to address some of these issues and provide further scaling opportunities.
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23 Oct 2009TL;DR: In this paper, a surrogate response surface model (RSM) was developed for peripheral n-type field-effect transistors in a dynamic random-access-memory process flow to identify, model, and analyze process variation.
Abstract: Reduction of electrical parameter variation is essential to achieve high yield and reliability in semiconductor devices. However, variation depends on a large number of process factors, which are often interdependent. In this work, well-calibrated Technology Computer-Aided-Design process and device simulations were performed in a designed experiment to develop an efficient, surrogate response surface model (RSM) of the device parameters as a function of key process factors. Monte Carlo simulations were performed with the RSM to estimate variation and design systems to reduce variation. The approach, illustrated here specifically for peripheral n-type field-effect transistors in a dynamic random-access-memory process flow, is general, easy-to-implement, and a cost-effective way to systematically identify, model, and analyze process variation.
3 citations
Cites methods from "Trends in memory technology - relia..."
...Here, the processes are optimized to improve the retention time of memory cells [7]....
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TL;DR: Tunneling barrier engineered charge trap flash (TBE-CTF) memory devices were fabricated using the tunneling barrier engineering technique Variable oxide thickness (VARIOT) barrier and CRESTed barrier consisting of thin SiO 2 and Si 3 N 4 dielectric layers were used as engineered tunneling barriers as discussed by the authors.
3 citations
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02 May 2010TL;DR: In this paper, the authors present an optimal cell design for the improved reliability characteristics in the level of mass production for the future NAND Flash with floating gate cells, which is a simple way to relieve the short channel effect is increasing the channel boron concentration.
Abstract: One of the critical scaling barriers in sub 30 nm NAND Flash technology node is an abrupt threshold voltage drop of cell transistors by short channel effect. It increases program voltage which leads, in turn, to fatal reliability issues. A simple way to relieve the short channel effect is increasing the channel boron concentration. However it degrades endurance characteristics by deteriorating boosting efficiency on inhibit operation. In this paper, we present an optimal cell design for the improved reliability characteristics in the level of mass production for the future NAND Flash with floating gate cells.
1 citations
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25 Feb 2013References
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01 Feb 1995TL;DR: This work has shown that polynomials over Galois Fields, particularly the Hadamard, Quadratic Residue, and Golay Codes, are good candidates for Error Control Coding for Digital Communication Systems.
Abstract: 1. Error Control Coding for Digital Communication Systems. 2. Galois Fields. 3. Polynomials over Galois Fields. 4. Linear Block Codes. 5. Cyclic Codes. 6. Hadamard, Quadratic Residue, and Golay Codes. 7. Reed-Muller Codes 8. BCH and Reed-Solomon Codes. 9. Decoding BCH and Reed-Solomon Codes. 10. The Analysis of the Performance of Block Codes. 11. Convolutional Codes. 12. The Viterbi Decoding Algorithm. 13. The Sequential Decoding Algorithms. 14. Trellis Coded Modulation. 15. Error Control for Channels with Feedback. 16. Applications. Appendices: A. Binary Primitive Polynomials. B. Add-on Tables and Vector Space Representations for GF(8) Through GF(1024). C. Cyclotronic Cosets Modulo 2m-1. D. Minimal Polynomials for Elements in GF (2m). E. Generator Polynomials of Binary BCH Codes of Lengths Through 511. Bibliography.
1,944 citations
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15 May 2006TL;DR: The critical barriers in further scaling down NAND flash to 40nm technology node and beyond are reviewed and breakthrough technologies are addressed to overcome the barriers.
Abstract: The NAND flash memory occupied 40% of the total flash memory market with an annual growth rate of 70% in 2004, while NOR flash achieved only more modest growth rate of 30%. It is expected that NAND flash will surpass the market share of NOR flash in the flash market for the first time in 2005. From the viewpoint of market trend, NAND flash will be more popular in future because of more diversified applications such as NHDD (NAND-HDD) and sub-notebook PC storage. In this paper, we review the critical barriers in further scaling down NAND flash to 40nm technology node and beyond. Then, breakthrough technologies are addressed to overcome the barriers. In addition, issues in performance and reliability of the high density NAND flash are discussed
93 citations
"Trends in memory technology - relia..." refers background in this paper
...In a SLC design, erased cells have low camera, portable multimedia players and solid-state disk threshold voltage and programmed cells have high threshold. drives [1]....
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TL;DR: In this paper, a 3D electrostatic model and a modified Wentzel-Kramers-Brillouin tunneling model have been implemented to simulate the programming and retention characteristics of the metal nanocrystal (NC) memories.
Abstract: The three-dimensional (3D) electrostatics together with the modified Wentzel-Kramers-Brillouin tunneling model has been implemented to simulate the programming and retention characteristics of the metal nanocrystal (NC) memories. Good agreements with experimental data are first demonstrated to calibrate the transport parameters. In contrast to previous works, the 3D electrostatic effects investigated in this paper are proven very significant in the memory operations. Therefore, new design criteria of metal NC memories are investigated. Part I presents the physical model and the NC array design optimization. A sparse and large-size NC array, which is suitable for the one-dimensional narrow-channel memories, provides higher program/erase tunneling current density due to the field-enhancement effect and lower charging energy due to the large NC capacitance. On the other hand, to achieve a sufficient memory window, fast programming speed, and long retention time in the typical two-dimensional channel memories, a dense and large-size NC array is favorable while taking the tradeoff with the NC number density into account. Based on the same theoretical model, the authors continue in Part II to consider the design optimization when high-K dielectrics can be employed
78 citations
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TL;DR: A compact on-chip Error Correcting Code/Circuit (ECC) for low cost Flash memories has been developed to minimize the chip size increase.
Abstract: A compact on-chip error correcting circuit (ECC) for low cost flash memories has been developed. The total increase in chip area is 2%, including all cells, sense amplifiers, logic, and wiring associated with the ECC. The proposed on-chip ECC, employing 10 check bits for 512 data bits, has been implemented on an experimental 64M-bit NAND flash memory. The cumulative sector error rate has been improved from 10/sup -4/ to 10/sup -10/. By transferring read data from the sense amplifiers to the ECC twice, 522-Byte temporary buffers, which are required for the conventional ECC and occupy a large part of the ECC area, have been eliminated. As a result, the area for the circuit has been drastically reduced by a factor of 25. The proposed on-chip ECC has been optimized in consideration of balance between the reliability improvement and the cell area overhead. The power increase has been suppressed to less than 1 mA.
76 citations
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TL;DR: In this article, a chaperonin protein lattice can be used as a template to assemble nanocrystal arrays for flash memory fabrication, achieving high density of 95times1011/cm 2 and 16times1012/cm2, respectively.
Abstract: For the first time, we demonstrate that a chaperonin protein lattice can be used as a template to assemble nanocrystal (NC) arrays for Flash memory fabrication This provides a new approach that can incorporate different types of NCs from a colloidal suspension for Flash memory fabrication Lead selenide and cobalt NC assemblies achieved through this method have a high density of 95times1011/cm 2 and 16times1012/cm2, respectively, as well as good distribution uniformity Devices exhibit promising Flash memory functions, with a flatband shift of 05 under 8-V operation, endurance >105 cycles, and retention time >104 s
41 citations