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Journal ArticleDOI: 10.1109/JETCAS.2014.2361068

Tunnel FET RF Rectifier Design for Energy Harvesting Applications

22 Oct 2014-IEEE Journal on Emerging and Selected Topics in Circuits and Systems (IEEE)-Vol. 4, Iss: 4, pp 400-411
Abstract: Radio-frequency (RF)-powered energy harvesting systems have offered new perspectives in various scientific and clinical applications such as health monitoring, bio-signal acquisition, and battery-less data-transceivers. In such applications, an RF rectifier with high sensitivity, high power conversion efficiency (PCE) is critical to enable the utilization of the ambient RF signal power. In this paper, we explore the high PCE advantage of the steep-slope III-V heterojunction tunnel field-effect transistor (HTFET) RF rectifiers over the Si FinFET baseline design for RF-powered battery-less systems. We investigate the device characteristics of HTFETs to improve the sensitivity and PCE of the RF rectifiers. Different topologies including the two-transistor (2-T) and four-transistor (4-T) complementary-HTFET designs, and the n-type HTFET-only designs are evaluated with design parameter optimizations to achieve high PCE and high sensitivity. The performance evaluation of the optimized 4-T cross-coupled HTFET rectifier has shown an over 50% PCE with an RF input power ranging from -40 dBm to -25 dBm, which significantly extends the RF input power range compared to the baseline Si FinFET design. A maximum PCE of 84% and 85% has been achieved in the proposed 4-T N-HTFET-only rectifier at -33.7 dBm input power and the 4-T cross-coupled HTFET rectifier at -34.5 dBm input power, respectively. The capability of obtaining a high PCE at a low RF input power range reveals the superiority of the HTFET RF rectifiers for battery-less energy harvesting applications.

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Topics: Rectifier (54%), Radio frequency (50%)
Citations
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Proceedings ArticleDOI: 10.1145/2744769.2747910
Yongpan Liu1, Zewei Li1, Hehe Li1, Yiqun Wang1  +8 moreInstitutions (4)
07 Jun 2015-
Abstract: Energy harvesting is gaining more and more attentions due to its characteristics of ultra-long operation time without maintenance. However, frequent unpredictable power failures from energy harvesters bring performance and reliability challenges to traditional processors. Nonvolatile processors are promising to solve such a problem due to their advantage of zero leakage and efficient backup and restore operations. To optimize the nonvolatile processor design, this paper proposes new metrics of nonvolatile processors to consider energy harvesting factors for the first time. Furthermore, we explore the nonvolatile processor design from circuit to system level. A prototype of energy harvesting nonvolatile processor is set up and experimental results show that the proposed performance metric meets the measured results by less than 6.27% average errors. Finally, the energy consumption of nonvolatile processor is analyzed under different benchmarks.

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Topics: Energy consumption (55%), Energy harvesting (51%), Processor design (50%) ...read more

105 Citations


Journal ArticleDOI: 10.1109/TCAD.2015.2446937
Yiqun Wang1, Yongpan Liu1, Cong Wang, Zewei Li1  +4 moreInstitutions (3)
Abstract: Energy harvesting from natural environment gives range of benefits for the Internet of things. Scavenging energy from photovoltaic (PV) cells is one of the most practical solutions in terms of power density among existing energy harvesting sources. PV power systems mandate the maximum power point tracking (MPPT) to scavenge the maximum possible solar energy. In general, a switching-mode power converter, an MPPT charger, controls the charging current to the energy storage element (a battery or equivalent), and the energy storage element provides power to the load device. The mismatch between the maximum power point (MPP) current and the load current is managed by the energy storage element. However, such architecture causes significant energy loss (typically over 20%) and a significant weight/volume and a high cost due to the cascaded power converters and the energy storage element. This paper pioneers a converter-less PV power system with the MPPT that directly supplies power to the load without the power converters or the energy storage element. The proposed system uses a nonvolatile microprocessor to enable an extremely fine-grain dynamic power management in a few hundred microseconds. This makes it possible to match the load current with the MPP current. We present detailed modeling, simulation, and optimization of the proposed energy harvesting system including the radio frequency transceiver. Experiments show that the proposed setup achieves an 87.1% of overall system efficiency during a day, 30.6% higher than the conventional MPPT methods in actual measurements, and thus a significantly higher duty cycle under a weak solar irradiance.

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Topics: Maximum power point tracking (69%), Power optimizer (64%), Energy storage (63%) ...read more

72 Citations


Open accessJournal ArticleDOI: 10.1109/ACCESS.2016.2526622
Kun Yang1, Qin Yu2, Supeng Leng2, Bo Fan2  +1 moreInstitutions (2)
08 Feb 2016-IEEE Access
Abstract: This paper describes a new type of communication network called data and energy integrated communication networks (DEINs), which integrates the traditionally separate two processes, i.e., wireless information transfer (WIT) and wireless energy transfer (WET), fulfilling co-transmission of data and energy. In particular, the energy transmission using radio frequency is for the purpose of energy harvesting (EH) rather than information decoding. One driving force of the advent of DEINs is wireless big data, which comes from wireless sensors that produce a large amount of small piece of data. These sensors are typically powered by battery that drains sooner or later and will have to be taken out and then replaced or recharged. EH has emerged as a technology to wirelessly charge batteries in a contactless way. Recent research work has attempted to combine WET with WIT, typically under the label of simultaneous wireless information and power transfer. Such work in the literature largely focuses on the communication side of the whole wireless networks with particular emphasis on power allocation. The DEIN communication network proposed in this paper regards the convergence of WIT and WET as a full system that considers not only the physical layer but also the higher layers, such as media access control and information routing. After describing the DEIN concept and its high-level architecture/protocol stack, this paper presents two use cases focusing on the lower layer and the higher layer of a DEIN network, respectively. The lower layer use case is about a fair resource allocation algorithm, whereas the high-layer section introduces an efficient data forwarding scheme in combination with EH. The two case studies aim to give a better explanation of the DEIN concept. Some future research directions and challenges are also pointed out.

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Topics: Wireless network (61%), Wireless sensor network (60%), Wireless (55%) ...read more

59 Citations


Open accessJournal ArticleDOI: 10.1109/JEDS.2015.2412118
Abstract: Tunnel field effect transistors (TFETs) have emerged as one of the most promising post-CMOS transistor technologies. In this paper, we: 1) review the perspectives of such devices for low-power high-frequency analog integrated circuit applications (e.g., GHz operation with sub-0.1 mW power consumption); 2) discuss and employ a compact TFET device model in the context of the $g_{m}/I_{d}$ integrated analog circuit design methodology; and 3) compare several proposed TFET technologies for such applications. The advantages of TFETs arise since these devices can operate in the sub-threshold region with larger transconductance-to-current ratio than traditional FETs, which is due to the current turn-on mechanism being interband tunneling rather than thermionic emission. Starting from technology computer-aided design and/or analytical models for Si-FinFETs, graphene nano-ribbon (GNR) TFETs and InAs/GaSb TFETs at the 15-nm gate-length node, as well as InAs double-gate TFETs at the 20-nm gate-length node, we conclude that GNR TFETs might promise larger bandwidths at low-voltage drives due to their high current densities in the sub-threshold region. Based on this analysis and on theoretically predicted properties, GNR TFETs are identified as one of the most attractive field effect transistor technologies proposed-to-date for ultra-low power analog applications.

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Topics: MOSFET (52%), Field-effect transistor (51%), Transistor (51%) ...read more

49 Citations


Open accessJournal ArticleDOI: 10.1109/TMSCS.2016.2519022
Wei-Yu Tsai1, Xueqing Li1, Matthew Jerry1, Baihua Xie1  +11 moreInstitutions (6)
01 Jan 2016-
Abstract: High power consumption has significantly increased the cooling cost in high-performance computation stations and limited the operation time in portable systems powered by batteries. Traditional power reduction mechanisms have limited traction in the post-Dennard Scaling landscape. Emerging research on new computation devices and associated architectures has shown three trends with the potential to greatly mitigate current power limitations. The first is to employ steep-slope transistors to enable fundamentally more efficient operation at reduced supply voltage in conventional Boolean logic, reducing dynamic power. The second is to employ brain-inspired computation paradigms, directly embodying computation mechanisms inspired by the brains, which have shown potential in extremely efficient, if approximate, processing with silicon-neuron networks. The third is “let physics do the computation”, which focuses on using the intrinsic operation mechanism of devices (such as coupled oscillators) to do the approximate computation, instead of building complex circuits to carry out the same function. This paper first describes these three trends, and then proposes the use of the hybrid-phase-transition-FET (Hyper-FET), a device that could be configured as a steep-slope transistor, a spiking neuron cell, or an oscillator, as the device of choice for carrying these three trends forward. We discuss how a single class of device can be configured for these multiple use cases, and provide in-depth examination and analysis for a case study of building coupled-oscillator systems using Hyper-FETs for image processing. Performance benchmarking highlights the potential of significantly higher energy efficiency than dedicated CMOS accelerators at the same technology node.

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Topics: Node (circuits) (53%), Dynamic demand (52%), Computation (52%) ...read more

29 Citations


References
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Journal ArticleDOI: 10.1109/JPROC.2010.2070470
Alan Seabaugh1, Qin Zhang1Institutions (1)
25 Oct 2010-
Abstract: Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.

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Topics: Tunnel field-effect transistor (65%), Logic gate (55%), MOSFET (54%) ...read more

1,272 Citations


Journal ArticleDOI: 10.1109/JSSC.2009.2028955
Koji Kotani1, A. Sasaki1, Takashi Ito1Institutions (1)
03 Nov 2009-
Abstract: A high-efficiency CMOS rectifier circuit for UHF RFIDs was developed. The rectifier has a cross-coupled bridge configuration and is driven by a differential RF input. A differential-drive active gate bias mechanism simultaneously enables both low ON-resistance and small reverse leakage of diode-connected MOS transistors, resulting in large power conversion efficiency (PCE), especially under small RF input power conditions. A test circuit of the proposed differential-drive rectifier was fabricated with 0.18 mu m CMOS technology, and the measured performance was compared with those of other types of rectifiers. Dependence of the PCE on the input RF signal frequency, output loading conditions and transistor sizing was also evaluated. At the single-stage configuration, 67.5% of PCE was achieved under conditions of 953 MHz, - 12.5 dBm RF input and 10 KOmega output load. This is twice as large as that of the state-of-the-art rectifier circuit. The peak PCE increases with a decrease in operation frequency and with an increase in output load resistance. In addition, experimental results show the existence of an optimum transistor size in accordance with the output loading conditions. The multi-stage configuration for larger output DC voltage is also presented.

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Topics: Precision rectifier (65%), CMOS (55%), Transistor (52%) ...read more

371 Citations


Journal ArticleDOI: 10.1109/JSSC.2011.2170633
Yu-Te Liao1, Huanfen Yao2, Andrew Lingley2, Babak A. Parviz2  +1 moreInstitutions (2)
Abstract: This paper presents a noninvasive wireless sensor platform for continuous health monitoring. The sensor system integrates a loop antenna, wireless sensor interface chip, and glucose sensor on a polymer substrate. The IC consists of power management, readout circuitry, wireless communication interface, LED driver, and energy storage capacitors in a 0.36-mm2 CMOS chip with no external components. The sensitivity of our glucose sensor is 0.18 μA·mm-2·mM-1. The system is wirelessly powered and achieves a measured glucose range of 0.05-1 mM with a sensitivity of 400 Hz/mM while consuming 3 μW from a regulated 1.2-V supply.

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Topics: Wireless sensor network (54%), Contact lens (54%)

349 Citations


Journal ArticleDOI: 10.1109/TCSI.2007.895229
Soumyajit Mandal1, Rahul Sarpeshkar1Institutions (1)
Abstract: We investigate theoretical and practical aspects of the design of far-field RF power extraction systems consisting of antennas, impedance matching networks and rectifiers. Fundamental physical relationships that link the operating bandwidth and range are related to technology dependent quantities like threshold voltage and parasitic capacitances. This allows us to design efficient planar antennas, coupled resonator impedance matching networks and low-power rectifiers in standard CMOS technologies (0.5-mum and 0.18-mum) and accurately predict their performance. Experimental results from a prototype power extraction system that operates around 950 MHz and integrates these components together are presented. Our measured RF power-up threshold (in 0.18-mum, at 1 muW load) was 6 muWplusmn10%, closely matching the predicted value of 5.2 muW.

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Topics: Impedance matching (59%), RF power amplifier (58%), Low-power electronics (56%) ...read more

274 Citations


Open accessJournal ArticleDOI: 10.1109/LED.2009.2028907
Abstract: We compare the transient response of double-gate thin-body-silicon interband tunnel field-effect transistor (TFET) with its metal-oxide-semiconductor field-effect transistor counterpart. Due to the presence of source side tunneling barrier, the silicon TFETs exhibit enhanced Miller capacitance, resulting in large voltage overshoot/undershoot in its large-signal switching characteristics. This adversely impacts the performance of Si TFETs for digital logic applications. It is shown that TFETs based on lower bandgap and lower density of states materials like indium arsenide show significant improvement in switching behavior due to its lower capacitance and higher ON current at reduced voltages.

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  • Fig. 4. (a) Capacitance–voltage characteristics of an InAs TFET showing the gate (Cgg), gate-to-source (Cgs), and gate-to-drain (Cgd) capacitances as a function of gate-to-source voltage VGS. Note that the supply voltage is VDD = 0.25 V. (b) Transient response characteristics of an InAs TFET inverter. InAs TFET exhibits a significantly smaller voltage overshoot/undershoot due to smaller Miller capacitance and higher ION compared to Si TFETs. The fall time delay is improved significantly to 1.1 ps.
    Fig. 4. (a) Capacitance–voltage characteristics of an InAs TFET showing the gate (Cgg), gate-to-source (Cgs), and gate-to-drain (Cgd) capacitances as a function of gate-to-source voltage VGS. Note that the supply voltage is VDD = 0.25 V. (b) Transient response characteristics of an InAs TFET inverter. InAs TFET exhibits a significantly smaller voltage overshoot/undershoot due to smaller Miller capacitance and higher ION compared to Si TFETs. The fall time delay is improved significantly to 1.1 ps.
  • Fig. 3. (a) Peak overshoot and fall time delay as functions of load capacitance CL for Si (a) MOSFET and (b) TFET inverters. Fall time delay is measured as the time interval between 50% of input (Vin) and 50% of output (Vout) voltages of the inverter in Fig. 2.
    Fig. 3. (a) Peak overshoot and fall time delay as functions of load capacitance CL for Si (a) MOSFET and (b) TFET inverters. Fall time delay is measured as the time interval between 50% of input (Vin) and 50% of output (Vout) voltages of the inverter in Fig. 2.
  • Fig. 2. (a) Simulation of Si Zener diode fitted to experimental data from Fair and Wivell [13]. (b) Transient response characteristics of silicon TFET- and MOSFET-based inverters. The load capacitance CL is set to zero in this simulation. (c) Inverter schematic showing the origin of the overshoot/undershoot in TFET. (d) Si TFET and Si MOSFET inverter VTCs.
    Fig. 2. (a) Simulation of Si Zener diode fitted to experimental data from Fair and Wivell [13]. (b) Transient response characteristics of silicon TFET- and MOSFET-based inverters. The load capacitance CL is set to zero in this simulation. (c) Inverter schematic showing the origin of the overshoot/undershoot in TFET. (d) Si TFET and Si MOSFET inverter VTCs.
  • Fig. 1. (a) DC IDS–VGS characteristics for p-type and n-type Si TFET and MOSFET. Inset shows the device schematic; the details are explained in the text. (b) Capacitance–voltage characteristics showing the gate (Cgg), gate-to-source (Cgs), and gate-to-drain (Cgd) capacitances as a function of gate-to-source voltage VGS for (b) Si MOSFET and (c) Si TFET.
    Fig. 1. (a) DC IDS–VGS characteristics for p-type and n-type Si TFET and MOSFET. Inset shows the device schematic; the details are explained in the text. (b) Capacitance–voltage characteristics showing the gate (Cgg), gate-to-source (Cgs), and gate-to-drain (Cgd) capacitances as a function of gate-to-source voltage VGS for (b) Si MOSFET and (c) Si TFET.
Topics: MOSFET (56%), Capacitance (55%), Field-effect transistor (54%) ...read more

182 Citations


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