Journal ArticleDOI
Tunneling Field-Effect Transistor: Capacitance Components and Modeling
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TLDR
In this paper, a numerical simulation study of gate capacitance components in a tunneling field effect transistor (TFET) was performed, showing key differences in the partitioning of gate capacitor between the source and drain as compared with a MOSFET.Abstract:
We report a numerical simulation study of gate capacitance components in a tunneling field-effect transistor (TFET), showing key differences in the partitioning of gate capacitance between the source and drain as compared with a MOSFET. A compact model for TFET capacitance components, including parasitic and inversion capacitances, was built and calibrated with computer-aided design data. This model should be useful for further investigation of performance of circuits containing TFETs. The dependence of gate-drain capacitance Cgd on drain design and gate length was further investigated for reduction of switching delay in TFETs.read more
Citations
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Journal ArticleDOI
Controlling Ambipolar Current in Tunneling FETs Using Overlapping Gate-on-Drain
TL;DR: In this article, the authors demonstrated that overlapping the gate on the drain can suppress the ambipolar conduction, which is an inherent property of a tunnel field effect transistor (TFET).
Journal ArticleDOI
Effect of Drain Doping Profile on Double-Gate Tunnel Field-Effect Transistor and its Influence on Device RF Performance
TL;DR: In this article, the effect of drain doping profile on a double-gate tunnel field effect transistor (DG-TFET) and its radio-frequency (RF) performances was investigated.
Journal ArticleDOI
Tunnel Field-Effect Transistors for Analog/Mixed-Signal System-on-Chip Applications
TL;DR: In this article, the analog performance of a double-gate n-type tunnel field effect transistor (n-TFET) with a relatively small body thickness (10 nm) was investigated.
Journal ArticleDOI
Universal analytic model for tunnel FET circuit simulation
TL;DR: In this article, a simple analytic model based on the Kane-Sze formula is used to describe the currentvoltage characteristics of tunnel field effect transistors (TFETs), including the decrease in subthreshold swing with drain current and the superlinear onset of the output characteristic.
Journal ArticleDOI
An Analytical Charge Model for Double-Gate Tunnel FETs
TL;DR: In this article, an analytical charge model for double gate (DG) tunnel FETs was proposed, where the TFET was split into a series combination of a gated tunnel diode and a DG MOSFET.
References
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Proceedings ArticleDOI
Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and ≪60mV/dec subthreshold slope
TL;DR: In this paper, a Double-Gate, Strained-Ge, Heterostructure Tunneling FET (TFET) exhibiting very high drive currents and SS < 60 mV/dec was experimentally demonstrated.
Journal ArticleDOI
Performance Comparison Between p-i-n Tunneling Transistors and Conventional MOSFETs
TL;DR: In this paper, a detailed performance comparison between conventional n-i-n MOSFET transistors and tunneling field effect transistors (TFETs) is presented, using semiconducting carbon nanotubes as the model channel material.
Journal ArticleDOI
Comparing carbon nanotube transistors - the ideal choice: a novel tunneling device design
TL;DR: In this article, three different carbon nanotube (CN) field effect transistor (CNFET) designs are compared by simulation and experiment, and the authors explore the possibility of using CNs as gate-controlled tunneling devices.
Proceedings Article
Germanium-source tunnel field effect transistors with record high I ON /I OFF
TL;DR: Tunnel field effect transistors (TFETs) with record high I ON /I OFF ratio (≫106) for lowvoltage (0.5V) operation are achieved by using germanium in the source region to achieve a small tunnel bandgap.
Proceedings ArticleDOI
Impact of SOI, Si 1-x Ge x OI and GeOI substrates on CMOS compatible Tunnel FET performance
F. Mayer,C. Le Royer,J.-F. Damlencourt,K. Romanjek,Francois Andrieu,Claude Tabone,Bernard Previtali,Simon Deleonibus +7 more
TL;DR: In this article, the Drift Tunnel FET (DTFET) was proposed to solve the TFET bipolar parasitic conduction by a novel TFET architecture, with improved OFF state control, and demonstrated functional TFET and CMOS devices on Si1-xGexOI (x=15-30-100%) co-integrated with the same SOI process flow.