Turning silicon on its edge [double gate CMOS/FinFET technology]
IBM1
TL;DR: For both low-power and high-performance applications, DGCMOS-FinFET offers a most promising direction for continued progress in VLSI.
Abstract: Double-gate devices will enable the continuation of CMOS scaling after conventional scaling has stalled. DGCMOS/FinFET technology offers a tactical solution to the gate dielectric barrier and a strategic path for silicon scaling to the point where only atomic fluctuations halt further progress. The conventional nature of the processes required to fabricate these structures has enabled rapid experimental progress in just a few years. Fully integrated CMOS circuits have been demonstrated in a 180 nm foundry-compatible process, and methods for mapping conventional, planar CMOS product designs to FinFET have been developed. For both low-power and high-performance applications, DGCMOS-FinFET offers a most promising direction for continued progress in VLSI.
Citations
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Patent•
15 Dec 2003TL;DR: In this paper, a nonplanar semiconductor device and its method of fabrication is described, which includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate.
Abstract: A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
284 citations
Patent•
31 Mar 2004TL;DR: In this paper, a tri-gate transistor with stained enhanced mobility and its method of fabrication is presented, where a gate dielectric layer is formed on the semiconductor capping layer on the top surface of a semiconductor body and a gate electrode having a pair of laterally opposite sidewalls is formed around and around the gate dieslectric layers.
Abstract: A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed on a semiconductor substrate wherein the semiconductor body has a top surface on laterally opposite sidewalls. A semiconductor capping layer is formed on the top surface and on the sidewalls of the semiconductor body. A gate dielectric layer is formed on the semiconductor capping layer on the top surface of a semiconductor body and is formed on the capping layer on the sidewalls of the semiconductor body. A gate electrode having a pair of laterally opposite sidewalls is formed on and around the gate dielectric layer. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
284 citations
Patent•
30 Jun 2005TL;DR: In this article, a contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies is presented.
Abstract: A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.
221 citations
Patent•
27 Sep 2006TL;DR: In this article, a complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having at least two first gate electrodes comprising a first parameter, and an NMOS transistor with at least 2 second gate electrodes including a second parameter, wherein the second parameter is different than the first parameter.
Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having at least two first gate electrodes comprising a first parameter, and an NMOS transistor having at least two second gate electrodes comprising a second parameter, wherein the second parameter is different than the first parameter. The first parameter and the second parameter may comprise the thickness or the dopant profile of the gate electrode materials of the PMOS and NMOS transistors. The first and second parameter of the at least two first gate electrodes and the at least two second gate electrodes establish the work function of the PMOS and NMOS transistors, respectively.
180 citations
Patent•
01 Mar 2011TL;DR: In this paper, a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering is described.
Abstract: Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.
177 citations
References
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IBM1
TL;DR: This paper examines the apparent limits, possible extensions, and applications of CMOS technology in the nanometer regime from the point of view of device physics, device technology, and power consumption and speculate on the future ofCMOS for the coming 15-20 years.
Abstract: This paper examines the apparent limits, possible extensions, and applications of CMOS technology in the nanometer regime. Starting from device scaling theory and current industry projections, we analyze the achievable performance and possible limits of CMOS technology from the point of view of device physics, device technology, and power consumption. Various possible extensions to the basic logic and memory devices are reviewed, with emphasis on novel devices that are structurally distinct front conventional bulk CMOS logic and memory devices. Possible applications of nanoscale CMOS are examined, with a view to better defining the likely capabilities of future microelectronic systems. This analysis covers both data processing applications and nondata processing applications such as RF and imaging. Finally, we speculate on the future of CMOS for the coming 15-20 years.
381 citations
"Turning silicon on its edge [double..." refers background in this paper
...These structures may be classified into one of three basic categories [10] illustrated in Figure 8, namely: ✦ Type I, the planar DG, which is a direct extension of a planar CMOS process with a second, buried gate....
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01 Jan 1998
290 citations
"Turning silicon on its edge [double..." refers background in this paper
...Double-gate (DG) FETs, in which a second gate is added opposite the traditional (first) gate, have long been recognized [3], [4] for their potential to better control short-channel effects (SCEs)....
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TL;DR: In this article, a spacer patterning technology using a sacrificial layer and a chemical vapor deposition (CVD) spacer layer has been developed, and is demonstrated to achieve sub-7 nm structures with conventional dry etching.
Abstract: A spacer patterning technology using a sacrificial layer and a chemical vapor deposition (CVD) spacer layer has been developed, and is demonstrated to achieve sub-7 nm structures with conventional dry etching. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this technology yields critical dimension (CD) variations of minimum-sized features much smaller than that achieved by optical or e-beam lithography. In addition, it also provides a doubling of device density for a given lithography pitch. This method is used to pattern silicon fins for double-gate metal-oxide semiconductor field effect transistors (MOSFETs) (FinFETs) and gate electrode structures for ultrathin body MOSFETs. Process details are presented.
281 citations
"Turning silicon on its edge [double..." refers methods in this paper
...To etch the ultrathin (TSi = 15 nm) fins, spacer lithography [sidewall image transfer (SIT)] [17], [18] is used....
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03 Dec 1989
TL;DR: A fully depleted lean channel transistor (DELTA) with a gate structure and vertical ultrathin SOI (silicon-on-insulator) structure with selective field oxide is reported in this paper.
Abstract: A fully depleted lean channel transistor (DELTA) having a gate structure and vertical ultrathin SOI (silicon-on-insulator) structure with selective field oxide is reported In the deep submicron region, selective oxidation is useful for achieving SOI isolation It provides a high-quality crystal and a Si-SiO/sub 2/ interface as good as those of conventional bulk single-crystal devices Using experiments and simulation, it was shown that the gate structure of DELTA has effective channel controllability and its vertical ultrathin ( >
266 citations
"Turning silicon on its edge [double..." refers methods in this paper
...Recently, through use of the delta device [1], now commonly referred to as the FinFET [2], significant advances in DGCMOS device technology and performance have been demonstrated....
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IBM1
TL;DR: In this paper, a simulation-based analysis of device design at the 25 nm channel length generation is presented for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFETs.
Abstract: We present a simulation-based analysis of device design at the 25 nm channel length generation. Double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's are considered. Dependencies of short-channel effects on channel thickness and ground-plane bias are illustrated. Two-dimensional field effects in the gate insulator (high k) and the buried insulator (low k) in single-gate SOI are studied.
259 citations