Two phase sinusoidal power clocked quasi-static adiabatic logic families
20 Aug 2015-pp 503-508
TL;DR: The paper presents the comprehensive analysis and evaluation of static adiabatic logic circuits operated by two phase sinusoidal clock signals and shows that the 8-bit CLA carry look ahead adder realizes energy reduction from 45% to 83% over a frequency range of 100 KHz to 500MHz operation against the static CMOS implementation.
Abstract: The paper presents the comprehensive analysis and evaluation of static adiabatic logic circuits operated by two phase sinusoidal clock signals. The static adiabatic logic has an advantage in the form of reduction in switching energy while comparing with the dynamic adiabatic logic. This advantage is realized due to the fact that the discharging operation at a node happens only when the input signal transition demands a change in the state of the output. Or in other words, if the next input state happens to be the same as the present state, the charged output nodal state remains the same, without undergoing any recovery phase. The analysis of the static adiabatic logic is done using a carry look ahead adder (CLA) implemented by static adiabatic families, namely, QSERL, CEPAL, ASL and QSECRL and comparing them against the static CMOS counterpart. The performance of each of the circuit is studied in terms of the frequency and power clock voltage range of operation. The simulations show that the 8-bit CLA static adiabatic adder realizes energy reduction from 45% to 83% over a frequency range of 100 KHz to 500MHz operation against the static CMOS implementation. The analyses were carried out using SPICE EDA tools using 180 nm technology library from TSMC.
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01 Jan 2018
TL;DR: In this paper, an 8-bit Carry Look-ahead Adder is implemented and compared using two different types of designs—a conventional Complementary Metal-Oxide Semiconductor (CMOS) logic and an Efficient Charge Recovery Logic (ECRL).
Abstract: Full adders are the building blocks of nearly all the VLSI applications—be it digital signal processing or image and video processing. In this paper, an 8-bit Carry Look-ahead Adder is implemented and compared using two different types of designs—a conventional Complementary Metal-Oxide Semiconductor (CMOS) logic and an Efficient Charge Recovery Logic (ECRL). These adders are designed and simulated using Tanner Tools v15.23 with 180 nm technology. Performance parameters like power consumption and propagation delay are compared by varying input supply and operating frequency for the two different circuits. The comparison shows that an 8-bit CLA design using ECRL Adiabatic logic is better than an 8-bit CLA design using CMOS logic in terms of power consumption, transistor count, and power delay product (PDP).
1 citations
01 Jul 2017
TL;DR: A low power adiabatic Universal Shift Register, which can perform both serial and parallel shift operations, and DFAL circuits are analyzed based on transistor count, power dissipation and delay.
Abstract: In digital circuits, shift registers are used as the basic memory units. This paper presents a low power adiabatic Universal Shift Register, which can perform both serial and parallel shift operations. Since power dissipation is a critical factor many low power dissipation techniques have been proposed but most of these techniques have some trade-offs. Adiabatic logic technique as compared to that of a conventional CMOS technique shows promising results. A type of adiabatic technique, DFAL (Diode Free Adiabatic Logic), has been studied in this paper and NOR gate, NAND gate, XOR gate, D Flip-Flop and Universal Shift Register have been designed using this configuration. DFAL circuits are analyzed based on transistor count, power dissipation and delay. All the circuits are simulated in Pyxis (Mentor Graphics) 180nm technology at 1.8V.
Cites methods from "Two phase sinusoidal power clocked ..."
...Kanchana Bhaaskaran have presented a comprehensive analysis and evaluation of ASL (Adiabatic Static logic), QSERL (Quasi Static Energy Recovery Logic), CEPAL (Complementary Energy Path Adiabatic Logic) and QSECRL (Quasi Static Efficient Charge Recovery Logic)logic [6]....
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References
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TL;DR: Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic logic circuit and shows four to six times power reduction with a practical loading and operation frequency range.
Abstract: Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic logic circuit. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder (CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows four to six times power reduction with a practical loading and operation frequency range. An inductor-based supply clock generation circuit is proposed. Circuits are designed using 1.0-/spl mu/m CMOS technology with a reduced threshold voltage of 0.2 V.
503 citations
23 Apr 1995
TL;DR: This paper introduces a new class of adiabatic computing circuits which have several advantages over existing approaches, the primary one being that, because no diodes are used, switching energy can be reduced to an energy of O(CV t) over conventional CMOS.
Abstract: Recent advances in compact, practical adiabatic computing circuits which demonstrate signi cant energy savings have renewed interest in using such techniques in lowpower systems. Several recently introduced circuits for adiabatic computing make use of diodes in a way which reduces switching energy from O(CV dd) in the nonadiabatic (ie: standard CMOS) case, to O(CV ddV t). These circuits provide an energy savings of at most one order of V dd=V t. This paper introduces a new class of adiabatic computing circuits which o er several advantages over existing approaches, the primary one being that, because no diodes are used, switching energy can be reduced to an energy oor of O(CV t). These second order adiabatic computing circuits provide an energy savings of as much as O(V dd=V t) over conventional CMOS. Additional advantages of the proposed circuits include the fact that, in comparison to most compact adiabatic circuits which have oating output levels over the entire data valid time, these new circuits have nonoating output levels over most of the data valid time. This is important for restoring logic levels and minimizing problems with crosstalk. The proposed circuits have been simulated and demonstrate adiabatic power savings compared to standard CMOS circuits over an operating frequency range from 1MHz to 100MHz of as much as a factor of 3. One circuit topology has been fabricated and tested and operates properly at up to 100MHz, the maximum speed which could be tested. Power measurements on the functioning circuit are in progress and preliminary results demonstrate adiabatic power-vs-frequency behavior. These second order adiabatic computing circuits provide an attractive alternative to achieve adiabatic power savings without su ering from many of the limitations of alternative approaches and without costing much more either in terms of complexity or size.
213 citations
TL;DR: In this paper, an adiabatic logic family is presented, which makes use of a CMOS positive feedback amplifier, and a gate is based on dual rail logic and a cascade of such gates only needs three power/clock lines to operate.
Abstract: An adiabatic logic family is presented, which makes use of a CMOS positive feedback amplifier. The gate is based on dual rail logic and a cascade of such gates only needs three power/clock lines to operate. The positive feedback amplifier ensures high noise immunity and takes part in the energy recovery process.
176 citations
TL;DR: A new quasi-static energy recovery logic family (QSERL) using the principle of adiabatic switching is proposed in this paper, which uses two complementary sinusoidal supply clocks and resembles the behavior of static CMOS.
Abstract: A new quasi-static energy recovery logic family (QSERL) using the principle of adiabatic switching is proposed in this paper. Most of the previously proposed adiabatic logic styles are dynamic and require complex clocking schemes. The proposed QSERL uses two complementary sinusoidal supply clocks and resembles the behavior of static CMOS. Thus, switching activity is significantly lower than dynamic logic. In addition, QSERL circuits can be directly derived from static CMOS circuits. A high-efficiency clock generation circuitry, which generates two complementary sinusoidal clocks compatible to QSERL, is also presented in this paper. The adiabatic clock circuitry locks the frequency of clock signals, which makes it possible to integrate adiabatic modules into a VLSI system. We have designed an 8/spl times/8 carry-save multiplier using QSERL logic and two phase sinusoidal clocks. SPICE simulation shows that the QSERL multiplier can save 34% of energy over static CMOS multiplier at 100 MHz.
131 citations
09 Jun 1994
TL;DR: In this paper, the authors considered the 2N-2N-N2D shift register ring and showed how to recover over 75% of the energy dissipation of the clock.
Abstract: Low-energy computing is an idea whose time has come. Applications include the smallest systems (where battery size and weight are crucial) as well as the largest systems (where power supply and cooling are crucial). To turn an F E T on or off requires transferring a certain amount of energy (the switching energy). The energy dissipated during this transfer need not be related to the energy transferred, but in ordinary CMOS logic circuits both quantities are on the order of $CV,2,, where C is the capacitance of a typical node, and V d d is the operating voltage. This level of dissipation is unavoidable if a l l the needed electrons are extracted from the V d d terminal of the power supply and ret,urned to the ground terminal. The essential idea of adiabatic computing is to construct circuits that allow each needed electron to be extracted at the lowest feasible voltage and returned at the highest feasible voltage. Ramp-like power/clock signals are required. Obviously it is advantageous to reduce c and V d d , but there are limits; in any case for the purposes of this paper we take such reductions for granted and show how dissipation can be further reduced at any particular V d d and c. The theoretical limit on dissipation is 0 for logically reversible operations, and kT for logically irreversible operations (1). Since kT is six or seven orders of magnitude below present-day values of $CV2d, there is considerable room for compromise. The logic family considered here, which we call 2N-2N2D, emphasizes overall system feasibility and throughput, while providing energy savings of “only” half an order of magnitude or so. Unlike previous diode-based energy recovery schemes (2; 3; 4) our major design goal was to present a nearly constant, data-independent capacitive load to the clock even though it makes 2N-2N2D about twice as complex as 1T1D (4). Constant load is vital, permitting operation from “stored energy” clock drivers. We have detailed simulations of such a clock driving a 6000-bit 2N-2N2D shift register ring, recovering over 75% of the transferred energy.
129 citations