Two-Stage Newton–Raphson Method for Transistor-Level Simulation
01 May 2007-IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE)-Vol. 26, Iss: 5, pp 881-895
TL;DR: An efficient transistor-level simulation tool with SPICE-accuracy for deep-submicrometer very large-scale integration circuits with strong-coupling effects with orders-of-magnitude speedup over Berkeley SPICE3 is observed.
Abstract: In this paper, we introduce an efficient transistor-level simulation tool with SPICE-accuracy for deep-submicrometer very large-scale integration circuits with strong-coupling effects. The new approach uses multigrid for huge networks of power/ground, clock, and interconnect with strong coupling. Mutual inductance can be incorporated without error-prone matrix sparsification approximations or expensive matrix inversion. Transistor devices are integrated using a novel two-stage Newton-Raphson method to dynamically model the linear network and nonlinear devices boundary. Orders-of-magnitude speedup over Berkeley SPICE3 is observed for sets of real deep-submicrometer design circuits
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Book•
11 Mar 2009TL;DR: EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits.
Abstract: This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book.
Covers complete spectrum of the EDA flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test - helps EDA newcomers to get "up-and-running" quickly
Includes comprehensive coverage of EDA concepts, principles, data structures, algorithms, and architectures - helps all readers improve their VLSI design competence
Contains latest advancements not yet available in other books, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - helps readers to design/develop testable chips or products
Includes industry best-practices wherever appropriate in most chapters - helps readers avoid costly mistakes
Table of Contents
Chapter 1: Introduction Chapter 2: Fundamentals of CMOS Design Chapter 3: Design for Testability Chapter 4: Fundamentals of Algorithms Chapter 5: Electronic System-Level Design and High-Level Synthesis Chapter 6: Logic Synthesis in a Nutshell Chapter 7: Test Synthesis Chapter 8: Logic and Circuit Simulation Chapter 9:?Functional Verification Chapter 10: Floorplanning Chapter 11: Placement Chapter 12: Global and Detailed Routing Chapter 13: Synthesis of Clock and Power/Ground Networks Chapter 14: Fault Simulation and Test Generation.
200 citations
TL;DR: An adaptive sparse matrix solver called NICSLU is proposed, which uses a multithreaded parallel LU factorization algorithm on shared-memory computers with multicore/multisocket central processing units to accelerate circuit simulation.
Abstract: The sparse matrix solver has become a bottleneck in simulation program with integrated circuit emphasis (SPICE)-like circuit simulators. It is difficult to parallelize the solver because of the high data dependency during the numeric LU factorization and the irregular structure of circuit matrices. This paper proposes an adaptive sparse matrix solver called NICSLU, which uses a multithreaded parallel LU factorization algorithm on shared-memory computers with multicore/multisocket central processing units to accelerate circuit simulation. The solver can be used in all the SPICE-like circuit simulators. A simple method is proposed to predict whether a matrix is suitable for parallel factorization, such that each matrix can achieve optimal performance. The experimental results on 35 matrices reveal that NICSLU achieves speedups of 2.08× ~ 8.57×(on the geometric mean), compared with KLU, with 1-12 threads, for the matrices which are suitable for the parallel algorithm. NICSLU can be downloaded from http://nicslu.weebly.com.
66 citations
Cites methods from "Two-Stage Newton–Raphson Method for..."
...Similar to the hierarchical method in [36], some multilevel Newton–Raphson methods are proposed in [37]–[39]....
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TL;DR: A transient simulator that allows for the simulation of an integrated circuit including both nonlinear devices and the layout of the linear network in linear complexity, and permits an almost embarrassingly parallel implementation on a many-core computing platform, and hence enabling linear speedup.
Abstract: In this paper, guided by electromagnetics-based first principles, the authors develop a transient simulator that allows for the simulation of an integrated circuit including both nonlinear devices and the layout of the linear network in linear complexity. The proposed circuit simulator rigorously captures the coupling between nonlinear circuits and the linear network. In addition, it bypasses the step of circuit extraction, producing a resistor-inductor-capacitor representation of the linear network without any numerical computation. Moreover, it permits an almost embarrassingly parallel implementation on a many-core computing platform, and hence enabling linear speedup. Application to die-package co-simulation as well as very large-scale on-chip circuits involving over complementary metal-oxide semiconductor transistors and interconnects having hundreds of millions of unknowns has demonstrated the superior performance of the proposed first-principle-guided circuit simulator.
22 citations
TL;DR: Most recent numerical integration methods to improve traditional SPICE time integration schemes, which are based on linear multi-step and low order approximation for the circuit differential equation system are reported.
Abstract: SPICE (Simulation Program with Integrated Circuit Emphasis) is a widely used circuit simulation framework for integrated circuit designs. The basic skeleton of SPICE time domain simulation was derived from the versions developed in UC Berkeley during the 1970s. In this paper, we report most recent numerical integration methods to improve traditional SPICE time integration schemes, which are based on linear multi-step and low order approximation for the circuit differential equation system. Recently, matrix exponential based time domain simulation algorithms are being developed to address long-term issues in the standard numerical integration methods. We review the related techniques in matrix exponential based approaches and state several distinguished features in challenging simulation problems, such as linear power network analysis and nonlinear circuit system simulation (SPICEDiego). We believe that the matrix exponential approaches can shed new light on the research and development of future circuit simulation algorithmic systems.
17 citations
Cites background or methods from "Two-Stage Newton–Raphson Method for..."
...However, the skeleton of numerical time integration methods in SPICE was designed in the 1970s....
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...Since 2005, Prof. Kuh and our team at UC San Diego have collaborated on circuit simulation [2]–[4]....
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...When k = 1, the integration is also called a linear one-step method....
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Patent•
01 Sep 2009TL;DR: In this paper, a node order ranking of nodes in a netlist can be determined, and a hierarchical data structure can be built based on the node order partitioning, where intermediate node orders can be dynamically merged for simulation optimization.
Abstract: A method of simulating an integrated circuit design is provided. In this method, a node order ranking of nodes in a netlist can be determined. Circuits of the netlist can then be partitioned based on the node order ranking with both static current driving and dynamic current driving schemes. A hierarchical data structure can be built based on the node order partitioning. In one embodiment, intermediate node orders can be dynamically merged for simulation optimization. Then, the circuits can be re-partitioned based on one or more merged intermediate node orders. Solving and integration can be performed using the hierarchical data structure to generate an order-ranked hierarchy engine. Analysis on the order-ranked hierarchy engine can be performed. At this point, simulation data of the IC design can be exported based on the analysis. By using this method, linear network reduction with its attendant accuracy loss is unnecessary.
13 citations
References
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TL;DR: Numerical experiments indicate that the new variant of Bi-CG, named Bi- CGSTAB, is often much more efficient than CG-S, so that in some cases rounding errors can even result in severe cancellation effects in the solution.
Abstract: Recently the Conjugate Gradients-Squared (CG-S) method has been proposed as an attractive variant of the Bi-Conjugate Gradients (Bi-CG) method. However, it has been observed that CG-S may lead to a rather irregular convergence behaviour, so that in some cases rounding errors can even result in severe cancellation effects in the solution. In this paper, another variant of Bi-CG is proposed which does not seem to suffer from these negative effects. Numerical experiments indicate also that the new variant, named Bi-CGSTAB, is often much more efficient than CG-S.
4,722 citations
TL;DR: In this article, an algorithm for generating provably passive reduced-order N-port models for linear RLC interconnect circuits is described, in which, in addition to macromodel stability, passivity is needed to guarantee the overall circuit stability.
Abstract: This paper describes an algorithm for generating provably passive reduced-order N-port models for RLC interconnect circuits. It is demonstrated that, in addition to macromodel stability, macromodel passivity is needed to guarantee the overall circuit stability once the active and passive driver/load models are connected. The approach proposed here, PRIMA, is a general method for obtaining passive reduced-order macromodels for linear RLC systems. In this paper, PRIMA is demonstrated in terms of a simple implementation which extends the block Arnoldi technique to include guaranteed passivity while providing superior accuracy. While the same passivity extension is not possible for MPVL, comparable accuracy in the frequency domain for all examples is observed.
1,465 citations
01 Jun 2000
1,302 citations
TL;DR: Sufficient conditions for convergence of the WR method are proposed and examples in MOS digital integrated circuits are given to show that these conditions are very mild in practice.
Abstract: The Waveform Relaxation (WR) method is an iterative method for analyzing nonlinear dynamical systems in the time domain. The method, at each iteration, decomposes the system into several dynamical subsystems each of which is analyzed for the entire given time interval. Sufficient conditions for convergence of the WR method are proposed and examples in MOS digital integrated circuits are given to show that these conditions are very mild in practice. Theoretical and computational studies show the method to be efficient and reliable.
834 citations
"Two-Stage Newton–Raphson Method for..." refers methods in this paper
...Waveform relaxation [ 22 ]–[24] is an iterative method that attempts to partition the circuit into subcircuits and repeatedly solve subcircuits by the relaxation of the nodal voltage waveform over time intervals....
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