Ultra low power 12-Bit SAR ADC for wireless sensing applications
01 Jan 2016-pp 1-4
TL;DR: The proposed SA-ADC operates for rail-to-rail input range and achieves low power consumption and a novel charge-integration based dynamic comparator are used forLow power consumption of the ADC.
Abstract: This paper presents a 12-bit SA-ADC for portable low power wireless sensor systems. The proposed SA-ADC operates for rail-to-rail input range and achieves low power consumption. Split capacitor array based DAC and a novel charge-integration based dynamic comparator are used for low power consumption of the ADC. Measured DNL and INL are −0.59/0.67 LSB and −1.2/1.33 LSB respectively. At sampling rate of 100-kS/s with 1.8-V supply, the ADC consumes only 2-μW power and achieves a SNDR of 64.42-dB, SFDR of 71.2-dB resulting in an FoM of 14-fJ/Conversion-step. The ADC core occupies an area of 0.238-mm2 and is fabricated in AMS 0.35-μm CMOS technology.
Citations
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TL;DR: An 8-bit 10 kS/s 0.3 V ultra-low power successive approximation register (SAR) analog-to-digital converter (ADC) is proposed and a presented double-bootstrapped switch with leakage reduction technologies improves sampling linearity under 0.
15 citations
Cites background from "Ultra low power 12-Bit SAR ADC for ..."
...Phase6 Phase7 Phase8 Phase3 Phase4 Phase5 Phase1 Phase2 D[1]=1 D[2]=1 D[3]=1 D[4]=0 D[5]=1 D[6]=1 D[7]=0 D[8]=1 T ra ns ie nt v ol ta ge...
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...Recently, ultra-lower power ADC used for sensor interfaces and wireless sensing applications have been presented in [4,5]....
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01 Jan 2011
9 citations
16 Mar 2018
TL;DR: It has been identified that the main component that causes a high power consumption in the circuit design is the dynamic comparator, which creates an impedance that can reduce the power consumption of the circuit considerably.
Abstract: 210MS/s 12-bit pipelined SAR ADC that can be used for mobile applications consists of various components that can reduce the precision and the power consumption of the device. It has been identified that the main component that causes a high power consumption in the circuit design is the dynamic comparator. The proposed design of the dynamic comparator shows a double tail dynamic comparator with an output buffer, which creates an impedance that can reduce the power consumption of the circuit considerably. The maximum power consumption of the comparator used is measured to be 402.3pW.
5 citations
Cites methods from "Ultra low power 12-Bit SAR ADC for ..."
...In this paper, a low power dynamic comparator design with an output buffer is proposed and is designed to meet the power requirements of a 12-bit pipelined SAR ADC designed for mobile applications [16]....
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18 Jun 2019
TL;DR: An analog-to-digital converter (ADC) which dynamically switches between high and low power modes in response to environmental noise is presented in order to promote power savings.
Abstract: Smart cities bring new technological advances that help improve everyday life. One such improvement is the ability to map out a city based on a characteristic. The amount of acoustic noise in an environment has many impacts on human life and has the potential to be collected wirelessly. Unfortunately, systems made today would not have the battery life capabilities to handle such a high demand if continuous transmission was used. In this paper, the design of a testbed for a smart microphone system is presented. In order to promote power savings, an analog-to-digital converter (ADC) which dynamically switches between high and low power modes in response to environmental noise is presented. Specifically, the high power ADC mode is triggered from a spike in the acoustic noise level. Ideally, this would be configurable and allow for detection of different types of sound such as human voice or music. A framework for basic environmental sound collection is presented along with preliminary results of the testbed.
5 citations
Cites background from "Ultra low power 12-Bit SAR ADC for ..."
...Authors in [6] describe a successive approximation ADC which targets low power wireless sen-...
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TL;DR: A high-performance digital interface application specific integrated circuit (ASIC) for triple-axis micro-electromechanical systems (MEMS) vibratory gyroscopes is presented, and the technique of time multiplexing is employed for synergetic stable drive control and precise angular velocity measurement in three separate degrees of freedom.
Abstract: This paper proposes a solution for sensing spatial angular velocity. A high-performance digital interface application specific integrated circuit (ASIC) for triple-axis micro-electromechanical systems (MEMS) vibratory gyroscopes is presented. The technique of time multiplexing is employed for synergetic stable drive control and precise angular velocity measurement in three separate degrees of freedom (DOF). Self-excited digital closed loop drives the proof mass in sensing elements at its inherent resonant frequency for Coriolis force generation during angular rotation. The analog front ends in both drive and sense loops are comprised of low-noise charge-voltage (C/V) converters and multi-channel incremental zoom analog-to-digital converters (ADC), so that capacitance variation between combs induced by mechanical motion is transformed into digital voltage signals. Other circuitry elements, such as loop controlling and accurate demodulation modules, are all implemented in digital logics. Automatic amplitude stabilization is mainly realized by peak detection and proportion-integration (PI) control. Nonlinear digital gain adjustment is designed for rapid establishment of resonance oscillation and linearity improvement. Manufactured in a standard 0.35-μm complementary metal-oxide-semiconductor (CMOS) technology, this design achieves a bias instability of 2.1°/h and a nonlinearity of 0.012% over full-scale range.
3 citations
References
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23 May 2005
TL;DR: A new method for switching the capacitors in the DAC capacitor array of a successive approximation register (SAR) ADC can be reduced by 37% compared to a conventional switching method by splitting the MSB capacitor into b - 1 binary scaled sub-capacitors.
Abstract: A new method for switching the capacitors in the DAC capacitor array of a successive approximation register (SAR) ADC is presented. By splitting the MSB capacitor into b - 1 binary scaled sub-capacitors, the average switching energy of the array can be reduced by 37% compared to a conventional switching method. A formal solution of the switching energy in four different switching methods is included, and the equations are verified using HSPICE simulations of a 10b capacitor array in a 0.18 /spl mu/m CMOS process.
344 citations
TL;DR: A resolution-rate scalable ADC for micro-sensor networks is described, based on the successive approximation register (SAR) architecture, which has two resolution modes: 12 bit and 8 bit, and its sampling rate is scalable, at a constant figure-of-merit, from 0-100 kS/s and 0-200 kS /s, respectively.
Abstract: A resolution-rate scalable ADC for micro-sensor networks is described. Based on the successive approximation register (SAR) architecture, this ADC has two resolution modes: 12 bit and 8 bit, and its sampling rate is scalable, at a constant figure-of-merit, from 0-100 kS/s and 0-200 kS/s, respectively. At the highest performance point (i.e., 12 bit, 100 kS/s), the entire ADC (including digital, analog, and reference power) consumes 25 muW from a 1-V supply. The ADC's CMRR is enhanced by common-mode independent sampling and passive auto-zero reference generation. The efficiency of the comparator is improved by an analog offset calibrating latch, and the preamplifier settling time is relaxed by self-timing the bit-decisions. Prototyped in a 0.18-mum, 5M2P CMOS process, the ADC, at 12 bit, 100 kS/s, achieves a Nyquist SNDR of 65 dB (10.55 ENOB) and an SFDR of 71 dB. Its INL and DNL are 0.68 LSB and 0.66 LSB, respectively
334 citations
01 Feb 2008
TL;DR: This SAR-ADC converter achieves 56fJ/conversion-step FOM with 58dB SNDR because it uses a comparator, named time-domainComparator, that instead of operating in the voltage domain, transforms the input and the reference voltages into pulses and compares their duration.
Abstract: The ADC-SAR is fabricated in a 0.18mum 2P5M CMOS process. This SAR-ADC converter achieves 56fJ/conversion-step FOM with 58dB SNDR. It uses a comparator, named time-domain comparator, that instead of operating in the voltage domain, transforms the input and the reference voltages into pulses and compares their duration.
241 citations
"Ultra low power 12-Bit SAR ADC for ..." refers background in this paper
...Instead of lowering the supply voltage, various circuit schemes [1-6] have been proposed to reduce the power consumption in ADCs by scaling of sampling rate, reducing the number of boosted switches, charge-based schemes and time-domain comparator....
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24 Sep 2007
TL;DR: An 8-bit successive approximation (SA) analog-to- digital converter (ADC) in 0.18 mum CMOS dedicated for energy-limited applications achieves a wide effective resolution bandwidth (ERBW) by applying only one bootstrapped switch, thereby preserving the desired low power characteristic.
Abstract: An 8-bit successive approximation (SA) analog-to- digital converter (ADC) in 0.18 mum CMOS dedicated for energy-limited applications is presented. The SA ADC achieves a wide effective resolution bandwidth (ERBW) by applying only one bootstrapped switch, thereby preserving the desired low power characteristic. Measurement results show that at a supply voltage of 0.9 V and an output rate of 200 kS/s, the SA ADC performs a peak signal-to-noise-and-distortion ratio of 47.4 dB and an ERBW up to its Nyquist bandwidth (100 kHz). It consumes 2.47 muW in the test, corresponding to a figure of merit of 65 f J/conversion-step.
206 citations
"Ultra low power 12-Bit SAR ADC for ..." refers background in this paper
...Instead of lowering the supply voltage, various circuit schemes [1-6] have been proposed to reduce the power consumption in ADCs by scaling of sampling rate, reducing the number of boosted switches, charge-based schemes and time-domain comparator....
[...]
TL;DR: A Data-Driven Noise-Reduction method is introduced to selectively enhance the comparator noise performance in a power-efficient 10/12 bit 40 kS/s SAR ADC for sensor applications.
Abstract: This paper presents a power-efficient 10/12 bit 40 kS/s SAR ADC for sensor applications. It supports resolutions of 10 and 12 bit and sample rates from DC up to 40 kS/s to accommodate a variety of sensor applications. A Data-Driven Noise-Reduction method is introduced to selectively enhance the comparator noise performance. In this way, a higher ADC resolution can be achieved with a small increase of the power consumption. A self-oscillating comparator is used to generate the bit-cycling clock internally. In this way, the ADC only requires an external clock at the sample-rate frequency. A segmented capacitive DAC with 250 aF unit elements is applied to save power and to reduce DNL errors at the same time. The implemented prototype in 65 nm CMOS occupies an area of 0.076 mm 2. For the two supported resolutions (10/12 bit), the ADC achieves an ENOB of 9.4 and 10.1 bit while consuming 72 and 97 nW from a 0.6 V supply at 40 kS/s. This leads to power efficiencies of 2.7 and 2.2 fJ/conversion-step for 10 bit and 12 bit resolution, respectively. Furthermore, the leakage power, which is below 0.4 nW, ensures that the efficiency can be maintained down to very low sample rates.
159 citations