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Proceedings ArticleDOI

Ultra low power, harsh environment SOI-CMOS design of temperature sensor based threshold detection and wake-up IC

18 Nov 2010-pp 1-2

AbstractAn ultra-low-power temperature-sensor-based silicon-on-insulator (SOI) CMOS Integrated Circuit (IC) for harsh environment application is presented. It first detects a temperature threshold, secondly generates a wake-up signal that turns on a data-acquisition microprocessor once the threshold has been detected and thirdly operates as a temperature sensor in a harsh environment while being wired to the microprocessor kept in a safe area. The IC is continuously on for a very long period of time and is required to be powered from a ultrathin battery type, hence must be an ultra low power design. It includes a diode-based temperature sensor, a quasi-temperature independent voltage generator, a comparator and a power switch to limit the microprocessor stand-by consumption. Since our application is mainly for harsh environment (e.g. high temperature, radiation), the chip has been designed using the 1-µm high-temperature SOI-CMOS XFAB technology; it occupies an area of 560µm×165µm. The biasing current and power dissipation are 4.12 µA and 20.6 µW respectively at a supply voltage of 5V and temperature of 27°C, according to the post-layout transistor level simulation results.

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Citations
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Patent
03 Aug 2012
Abstract: A method and apparatus for limiting access to an integrated circuit (IC) upon detection of abnormal conditions is provided. At least one of abnormal voltage detection, abnormal temperature detection, and abnormal clock detection are provided with low power consumption. Both abnormally low and abnormally high parameter values (e.g. abnormally low or high voltage, temperature, or clock frequency) may be detected. Abnormal clock detection may also detect a stopped clock signal, including a clock signal stopped at a low logic level or at a high logic level. Furthermore, abnormal clock detection may detect an abnormal duty cycle of a clock signal. A sampled bandgap reference may be used to provide accurate voltage and current references while consuming a minimal amount of power. Upon detection of an abnormal parameter value, one or more tamper indications may be provided to initiate tampering countermeasures, such as limiting access to the IC.

21 citations

Proceedings ArticleDOI
03 Mar 2014
TL;DR: The proposed capacitance readout interface circuit uses a sigma-delta technique to convert capacitance ratio into a digital output and is suitable to provide a high-accuracy digitized output for capacitive MEMS sensors.
Abstract: We present a capacitance readout interface circuit in bulk CMOS process which is functional at wide temperature range between -55oC to 175oC. The proposed circuit uses a sigma-delta technique to convert capacitance ratio into a digital output and is suitable to provide a high-accuracy digitized output for capacitive MEMS sensors. The circuit is implemented using IBM 0.13μm CMOS technology. Simulation results show that the circuit has excellent stability over wide temperature range, as high as 0.1% accuracy between -55oC to 175oC.

11 citations


Cites background from "Ultra low power, harsh environment ..."

  • ...As a result, most electronics for high temperature applications use either non-CMOS such as silicon carbide [9] or specialized CMOS process such as silicon on insulator technologies [10] which significantly reduce the leakage current at high temperatures....

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Journal ArticleDOI
Abstract: A novel contact resistive random access memory (CRRAM) device based a temperature sensor is proposed and investigated in this letter. By establishing the relationship between CRRAM's random telegraph noise (RTN) signal and temperature, a new temperature sensing scheme is demonstrated for the first time. With a simple comparator circuit, a digital output temperature sensor is successfully implemented based on the temperature-dependent RTN signal. The new sensing scheme is very suitable to low-power low-speed sensor modules.

11 citations

Proceedings ArticleDOI
19 Dec 2013
TL;DR: A CMOS capacitance to frequency convertor for capacitive MEMS sensors working in high temperature environments and has excellent stability over wide temperature range, good accuracy and high sensing resolution.
Abstract: We present a CMOS capacitance to frequency convertor for capacitive MEMS sensors working in high temperature environments. Many MEMS sensors are needed to work at the extended military temperature range from -55 oC to 175oC and require a suitable readout circuitry to detect, process, and transmit the sensor measurement data. The proposed CMOS circuitry uses a current to frequency conversion circuit to convert the sensor capacitance output into a digital output modulated in frequency. Pulse width control is implemented on-chip to control the pulse width of the output digital signal. The circuitry is implemented using IBM 0.13μm CMOS technology. Simulation results show that the circuitry has excellent stability over wide temperature range, good accuracy and high sensing resolution. The novelty in this work lies in the fact that a digital output is achieved without using complex analog to digital converter (ADC).

10 citations


Cites background from "Ultra low power, harsh environment ..."

  • ...Hence, currently most electronics for high temperature applications use either nonCMOS such as silicon carbide [11] or specialized CMOS such as silicon on insulator technologies [12] which significantly reduce the leakage current at high temperature....

    [...]

Journal ArticleDOI
TL;DR: The proposed Vth extraction circuit eliminates the nonlinear temperature-dependent mobility and mobility ratio terms, and it achieves a wide operating temperature range from -25 °C to 250 °C, and the ratiometric output achieves mean temperature inaccuracy within ±1.8% over a temperature of 275 °C.
Abstract: This brief presents a complementary-to-absolute-temperature voltage and a voltage reference based on the threshold voltage Vth extraction principle. The proposed Vth extraction circuit eliminates the nonlinear temperature-dependent mobility and mobility ratio terms, and it achieves a wide operating temperature range from -25 °C to 250 °C. The threshold-voltage temperature coefficient (TC) mismatch between nMOS and pMOS is compensated by selecting different channel lengths. Fabricated in the 1-μm partially depleted silicon-on-insulator CMOS process, the voltage reference achieves a box model TC of 27 parts per million (ppm) (mean) for an operating temperature range of -25 °C-250 °C and 18.7 ppm (mean) for a range of 25 °C-150 °C. Furthermore, the ratiometric output achieves mean temperature inaccuracy within ±1.8% over a temperature of 275 °C.

7 citations


Cites background from "Ultra low power, harsh environment ..."

  • ...The matching condition does not contain the mobility ratio factor, as in [9], [11], and [12]....

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  • ...The mobility ratio term for the reference voltage in [9] limits the operating temperature range since complete compensation is only achievable at a desired reference temperature; therefore, its application for temperature sensing is limited to temperature threshold detection [11], [12] at the reference temperature....

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References
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Book
22 Aug 1997
TL;DR: Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.
Abstract: The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

2,655 citations


"Ultra low power, harsh environment ..." refers background in this paper

  • ...0.5 °C). The comparator circuit is a traditional 3-stage based comparator [ 3 ], namely pre-amplification, decision and post-amplification stages; its biasing current is 2.11µA....

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Journal ArticleDOI
TL;DR: It is shown that bipolar substrate transis- tors are very suited to be applied to generate the basic and PTAT voltages and dynamic element matching and auto-calibration can solve the problems related to mismatching of components and noise.
Abstract: This paper reviews the concepts, opportunities and limitations of temperature sensors and voltage references realized in CMOS technology. It is shown that bipolar substrate transis- tors are very suited to be applied to generate the basic and PTAT voltages. Furthermore, it is shown that dynamic element matching and auto-calibration can solve the problems related to mismatching of components and noise. The effects of mechan- ical stress are a major source of inaccuracy. In CMOS technology, the mechanical-stress effects are small, as compared to those in bipolar technology. It is concluded that, with low-cost CMOS tech- nolog, rather accurate voltage references and temperature sensors can be realized.

199 citations


"Ultra low power, harsh environment ..." refers background in this paper

  • ...The diode-based temperature sensor [2] has a quasi-linear characteristic with a conversion rate of 5....

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Proceedings Article
01 Jan 2001
Abstract: A CMOS voltage reference, which takes advantage of weighted difference of the gate-source voltages between a PMOS and an NMOS transistor operating in saturation region, is presented in this paper. The reference has been implemented in a standard 0.6-µm CMOS process (V thn ≈ |V thp | ≈ 0.9 V@0° C) and gives a temperature coefficient of not greater than 62 ppm/°C from 0 to 100° C without trimming, while consuming a maximum of 9.7 µA with a minimum supply of 1.4 V. The worst-case line regulation is ±0.17 %/V. The occupied chip area is 0.055 mm2. The proposed reference has been applied to a 10-mA CMOS low dropout regulator, and a temperature coefficient of 94 ppm/°C is achieved when the regulator delivers maximum load current.

17 citations


"Ultra low power, harsh environment ..." refers background in this paper

  • ...It is based on weighted difference of gate-source voltages between PMOS and NMOS transistors operating in saturation region [1]....

    [...]

  • ...7 μA at 100 C in [1], by biasing the transistors in subthreshold operation....

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