Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance
01 Dec 2006-pp 1-4
TL;DR: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.
Abstract: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well
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TL;DR: By understanding the unique capabilities of carbon nanotubes and using them in unconventional designs, novel nanoelectronic applications may become feasible and much better control of materials quality must be obtained, and new fabrication processes must be developed before such applications can be realized.
Abstract: Carbon nanotube devices offer intrinsic advantages for high-performance logic device applications. The ultrasmall body of a carbon nanotube-the tube diameter-is the key feature that should allow aggressive channel length scaling, while the intrinsic transport properties of the nanotube ensure at the same time high on-currents. In addition, the narrowness of the tube is critical to implementation of novel device concepts like the tunneling transistor. By understanding the unique capabilities of carbon nanotubes and using them in unconventional designs, novel nanoelectronic applications may become feasible. However, much better control of materials quality must be obtained, and new fabrication processes must be developed before such applications can be realized.
358 citations
TL;DR: In this article, a 10-band sp3d5s* semi-empirical atomistic tight-binding model coupled to a self-consistent Poisson solver is used for the dispersion calculation.
Abstract: Bandstructure effects in the electronic transport of strongly quantized silicon nanowire field-effect-transistors (FET) in various transport orientations are examined. A 10-band sp3d5s* semiempirical atomistic tight-binding model coupled to a self-consistent Poisson solver is used for the dispersion calculation. A semi-classical, ballistic FET model is used to evaluate the current-voltage characteristics. It is found that the total gate capacitance is degraded from the oxide capacitance value by 30% for wires in all the considered transport orientations ([100], [110], [111]). Different wire directions primarily influence the carrier velocities, which mainly determine the relative performance differences, while the total charge difference is weakly affected. The velocities depend on the effective mass and degeneracy of the dispersions. The [110] and secondly the [100] oriented 3 nm thick nanowires examined, indicate the best ON-current performance compared to [111] wires. The dispersion features are strong functions of quantization. Effects such as valley splitting can lift the degeneracies particularly for wires with cross section sides below 3 nm. The effective masses also change significantly with quantization, and change differently for different transport orientations. For the cases of [100] and [111] wires the masses increase with quantization, however, in the [110] case, the mass decreases. The mass variations can be explained from the non-parabolicities and anisotropies that reside in the first Brillouin zone of silicon.
192 citations
TL;DR: The current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories are reviewed and the challenges and opportunities are outlined.
Abstract: Nanowire (NW) devices, particularly the gate-all-around (GAA) CMOS architecture, have emerged as the front-runner for pushing CMOS scaling beyond the roadmap. These devices offer unique advantages over their planar counterparts which make them feasible as an option for 22 -nm and beyond technology nodes. This paper reviews the current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories. We also take a glimpse into applications of NWs in the ldquomore-than-Moorerdquo regime and briefly discuss the application of NWs as biochemical sensors. Finally, we summarize the status and outline the challenges and opportunities of the NW technology.
164 citations
Cites background or methods from "Ultra-Narrow Silicon Nanowire Gate-..."
...NW FETs show excellent gate control, near-ideal subthreshold behavior, high ION/IOFF ratio, and high drive current [21], [27]–[ 29 ]....
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...The inset shows the NW channel before poly-gate deposition. Reprinted with permission from [ 29 ]....
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...(b) Drain current characteristics showing that high drive currents are possible in GAA FETs. Reprinted with permission from [ 29 ]....
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...The wires have been carefully released by etching away the grown oxide in dilute HF [28], [ 29 ]....
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...For instance, we obtained ION values of 2.4 and 1.3 mA/μm, DIBL values of 8 and 13 mV/V, and SS of 60 and 65 mV/dec for NMOS and PMOS, respectively [ 29 ]....
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TL;DR: The proposed silicon nanotube field effect transistor offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow.
Abstract: We introduce the concept of a silicon nanotube field effect transistor whose unique core–shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core–shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow.
140 citations
TL;DR: In this article, the scaling of nanowire transistors to 10-nm gate lengths and below is considered and compared with the published experimental data of nan-wire transistors, and the performance limit of a nan-ire transistor is assessed by applying a ballistic current model.
Abstract: This paper considers the scaling of nanowire transistors to 10-nm gate lengths and below. The 2-D scale length theory for a cylindrical surrounding-gate MOSFET is reviewed first, yielding a general guideline between the gate length and the nanowire size for acceptable short-channel effects. Quantum confinement of electrons in the nanowire is discussed next. It gives rise to a ground-state energy and, therefore, a threshold voltage dependent on the radius of the nanowire. The scaling limit of nanowire transistors hinges on how precise the nanowire size can be controlled. The performance limit of a nanowire transistor is then assessed by applying a ballistic current model. Key issues such as the density of states of the nanowire material are discussed. Comparisons are made between the model results and the published experimental data of nanowire devices.
138 citations
References
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TL;DR: In this article, a review highlights the recent advances in the field, using work from this laboratory for illustration, and the understanding of general nanocrystal growth mechanisms serves as the foundation for the rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks.
Abstract: ▪ Abstract Semiconductor nanowires and nanotubes exhibit novel electronic and optical properties owing to their unique structural one-dimensionality and possible quantum confinement effects in two dimensions. With a broad selection of compositions and band structures, these one-dimensional semiconductor nanostructures are considered to be the critical components in a wide range of potential nanoscale device applications. To fully exploit these one-dimensional nanostructures, current research has focused on rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks, and integration of nanowire elements into complex functional architectures. Significant progress has been made in a few short years. This review highlights the recent advances in the field, using work from this laboratory for illustration. The understanding of general nanocrystal growth mechanisms serves as the foundation for the rational sy...
1,407 citations
TL;DR: In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.
Abstract: This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.
605 citations
TL;DR: In this paper, a scaling theory for fully-depleted, cylindrical MOSFET's was presented. But the scaling theory was derived from the cylinrical form of Poisson's equation by assuming a parabolic potential in the radial direction.
Abstract: We present a scaling theory for fully-depleted, cylindrical MOSFET's. This theory was derived from the cylindrical form of Poisson's equation by assuming a parabolic potential in the radial direction. Numerical device simulation data for subthreshold slope and DIBL were compared to the model to validate the formula. By employing the scaling theory a comparison with double-gate (DG) MOSFET's was carried out illustrating an improvement of up to 40% in the minimum effective channel length for the cylindrical device.
551 citations
TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
Abstract: This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.
477 citations
TL;DR: In this paper, a general approach for the synthesis of a broad range of semiconductor nanowires (NWs) with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism was introduced.
Abstract: Semiconductor nanowires (NWs) represent an ideal system for investigating low- dimensional physics and are expected to play an important role as both interconnects and functional device elements in nanoscale electronic and optoelectronic devices Here we re- view a series of key advances defining a new paradigm of bottom-up assembling integrated nanosystems using semiconductor NW building blocks We first introduce a general ap- proach for the synthesis of a broad range of semiconductor NWs with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism Subsequently, we describe rational strategies for the hierarchical assembly of NW building blocks into functional devices and complex architectures based on electric field or micro-fluidic flow Next, we discuss a vari- ety of new nanoscale electronic device concepts including crossed NW p-n diode and crossed NW field effect transistors (FETs) Reproducible assembly of these scalable crossed NW de- vice elements enables a catalog of integrated structures, including logic gates and computa- tional circuits Lastly, we describe a wide range of photonic and optoelectronic devices, in- cluding nanoscale light-emitting diodes (nanoLEDs), multicolor LED arrays, integrated nanoLED-nanoFET arrays, single nanowire waveguide, and single nanowire nanolaser The potential application of these nanoscale light sources for chemical and biological analyses is discussed
252 citations