Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance
01 Dec 2006-pp 1-4
TL;DR: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.
Abstract: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well
Citations
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TL;DR: In this paper, the impact of precisely positioned dopants on the performance of ultimately scaled gate-all-around silicon nanowire transistors (NWTs) designed for digital circuit applications is investigated.
Abstract: In this paper, we report the first systematic study of quantum transport simulation of the impact of precisely positioned dopants on the performance of ultimately scaled gate-all-around silicon nanowire transistors (NWTs) designed for digital circuit applications. Due to strong inhomogeneity of the selfconsistent electrostatic potential, a full 3-D real-space nonequilibrium Green function formalism is used. The simulations are carried out for an n-channel NWT with 2.2 × 2.2 nm2 cross section and 6-nm channel length, where the locations of the precisely arranged dopants in the source-drain extensions and in the channel region have been varied. The individual dopants act as localized scatters, and hence, impact of the electron transport is directly correlated to the position of the single dopants. As a result, a large variation in the ON-current and a modest variation of the subthreshold slope are observed in the ID-VG characteristics when comparing devices with microscopically different discrete dopant configurations. The variations of the current-voltage characteristics are analyzed with reference to the behavior of the transmission coefficients.
23 citations
TL;DR: In this article, the performance of Si and InAs field effect transistors (NWFETs) in the ballistic transport model has been investigated using a first-principles calculation.
Abstract: In this paper, we study the band structures of Si and InAs nanowires based on a first-principles calculation and project performance potentials of Si and InAs nanowire field-effect-transistors (NWFETs) by using a semiclassical ballistic transport model. We demonstrate that the device performance of InAs NWFETs strongly depends on its cross-sectional dimension and gate oxide thickness. In particular, InAs NWFETs unexpectedly indicate lower current drivability than Si NWFETs as the gate oxide thickness is extremely scaled down to 0.5 nm in the ballistic limit. We discuss the mechanism in terms of operation in quantum capacitance limit (QCL). We also demonstrate that the advantage in the lower power operation with InAs NWFETs reduces when the devices operate in the QCL or higher subbands with a heavier transport effective mass participate in the transport.
22 citations
01 Dec 2007
TL;DR: In this article, a gate-all-around (GAA) silicon nanowire SONOS memory has been demonstrated for the first time, where Nitride and silicon nanocrystal (Si-NC) has been incorporated as the engineered charge trapping layer.
Abstract: Trap layer engineered gate-all-around (GAA) silicon nanowire SONOS memory showing excellent device performance is demonstrated for the first time. Nitride and silicon nanocrystal (Si-NC) has have been incorporated as the engineered charge trapping layer. Fast transient memory characteristic is shown owing to the nanowire channel structure. The device with embedded Si-NC achieves even faster higher memory speed and increased window, up to 3.2 V DeltaVth shift for 1 mus and 6.25 V memory window. The nanowire based non-volatile SONOS memory is promising for the future high speed and low power NAND-type flash memory application.
21 citations
Cites methods or result from "Ultra-Narrow Silicon Nanowire Gate-..."
...8 shows the Id-Vg characteristics for two kinds of SONOS devices (with and without TLE), with Lg~850 nm and diameter~5nm. Similar to previously reported Si-NW FETs [7], the vertically stacked twin Si-nanowire SONOS devices also exhibit excellent transfer characteristics....
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...After forming the Si nanowire [7], tunneling oxide, Si3N4 trapping layer and blocking oxide were deposited....
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...Similar to previously reported Si-NW FETs [7], the vertically stacked twin Si-nanowire SONOS devices also exhibit excellent transfer characteristics....
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TL;DR: In this paper, the transport properties of Si-nanowire (SiNW) field effect transistors have been investigated in a self-consistent approach based on the nonequilibrium Green's function (NEGF) scheme in the density functional theory framework.
Abstract: We report atomistic simulations of the transport properties of Si-nanowire (SiNW) field-effect transistors. Results have been obtained within a self-consistent approach based on the nonequilibrium Green's function (NEGF) scheme in the density functional theory framework. We analyze in detail the operation of an ultrascaled SiNW channel device and study the characteristics and transfer characteristics behavior of the device while varying several parameters including doping, gate and oxide lengths, and temperature. We focus our attention to the quantum capacitance of the SiNW and show that a well-tempered device design can be accomplished in this regime by choosing suitable doping profiles and gate contact parameters.
21 citations
Cites background or methods from "Ultra-Narrow Silicon Nanowire Gate-..."
...Although top–down approaches to SiNW technology have produced the best results in terms of device performance so far [5], bottom–up approaches have enabled a wide range of devices and integration strategies to be pursued....
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...gate-all-around (GAA) SiNW FET devices [5], recently obtained with a CMOS-compatible technology, show excellent...
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TL;DR: In this article, the integration of gate-all-around (GAA) nanowire (NW) transistors with low-resistivity metallic point contacts at source/drain extensions was demonstrated.
Abstract: This letter demonstrates successful integration of Gate-All-Around (GAA) nanowire (NW) transistors with low-resistivity metallic NW point contacts at source/drain extensions. Ultrascaled GAA silicon NW transistors with gate lengths down to 8 nm have been achieved, exhibiting good performance among the NW FETs reported to date. Compared to the reference devices, the metallic contact NW devices show 580% enhancement in I ON from 103 to 705 muA/mum , at a fixed I OFF of 10 nA/mum . Nickel silicide resistivity for ultrathin films is also investigated in this letter for the integration of salicided source/drain extensions with the GAA NW process. Experimental results show that 4 nm of deposited Ni is suitable for forming NW contacts with 10-nm diameters, which is thin enough to avoid oversilicidation while meeting the low-resistivity requirements.
20 citations
Cites methods from "Ultra-Narrow Silicon Nanowire Gate-..."
...N-channel GAA SiNW transistors were fabricated using a process flow similar to that reported in [2]....
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References
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TL;DR: In this article, a review highlights the recent advances in the field, using work from this laboratory for illustration, and the understanding of general nanocrystal growth mechanisms serves as the foundation for the rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks.
Abstract: ▪ Abstract Semiconductor nanowires and nanotubes exhibit novel electronic and optical properties owing to their unique structural one-dimensionality and possible quantum confinement effects in two dimensions. With a broad selection of compositions and band structures, these one-dimensional semiconductor nanostructures are considered to be the critical components in a wide range of potential nanoscale device applications. To fully exploit these one-dimensional nanostructures, current research has focused on rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks, and integration of nanowire elements into complex functional architectures. Significant progress has been made in a few short years. This review highlights the recent advances in the field, using work from this laboratory for illustration. The understanding of general nanocrystal growth mechanisms serves as the foundation for the rational sy...
1,407 citations
TL;DR: In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.
Abstract: This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.
605 citations
TL;DR: In this paper, a scaling theory for fully-depleted, cylindrical MOSFET's was presented. But the scaling theory was derived from the cylinrical form of Poisson's equation by assuming a parabolic potential in the radial direction.
Abstract: We present a scaling theory for fully-depleted, cylindrical MOSFET's. This theory was derived from the cylindrical form of Poisson's equation by assuming a parabolic potential in the radial direction. Numerical device simulation data for subthreshold slope and DIBL were compared to the model to validate the formula. By employing the scaling theory a comparison with double-gate (DG) MOSFET's was carried out illustrating an improvement of up to 40% in the minimum effective channel length for the cylindrical device.
551 citations
TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
Abstract: This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.
477 citations
TL;DR: In this paper, a general approach for the synthesis of a broad range of semiconductor nanowires (NWs) with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism was introduced.
Abstract: Semiconductor nanowires (NWs) represent an ideal system for investigating low- dimensional physics and are expected to play an important role as both interconnects and functional device elements in nanoscale electronic and optoelectronic devices Here we re- view a series of key advances defining a new paradigm of bottom-up assembling integrated nanosystems using semiconductor NW building blocks We first introduce a general ap- proach for the synthesis of a broad range of semiconductor NWs with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism Subsequently, we describe rational strategies for the hierarchical assembly of NW building blocks into functional devices and complex architectures based on electric field or micro-fluidic flow Next, we discuss a vari- ety of new nanoscale electronic device concepts including crossed NW p-n diode and crossed NW field effect transistors (FETs) Reproducible assembly of these scalable crossed NW de- vice elements enables a catalog of integrated structures, including logic gates and computa- tional circuits Lastly, we describe a wide range of photonic and optoelectronic devices, in- cluding nanoscale light-emitting diodes (nanoLEDs), multicolor LED arrays, integrated nanoLED-nanoFET arrays, single nanowire waveguide, and single nanowire nanolaser The potential application of these nanoscale light sources for chemical and biological analyses is discussed
252 citations