Proceedings ArticleDOI
Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance
Navab Singh,Fong Yin Lim,W. W. Fang,S. C. Rustagi,L. K. Bera,Ajay Agarwal,C.H. Tung,Keat-Mun Hoe,S. R. Omampuliyur,D. Tripathi,A. O. Adeyeye,Guo-Qiang Lo,N. Balasubramanian,Dim-Lee Kwong +13 more
- pp 1-4
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TLDR
Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.Abstract:
Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as wellread more
Citations
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Journal ArticleDOI
Effects of corner angle of trapezoidal and triangular channel cross-sections on electrical performance of silicon nanowire field-effect transistors with semi gate-around structure
Soshi Sato,Kuniyuki Kakushima,Parhat Ahmet,Kenji Ohmori,Kenji Natori,Keisaku Yamada,Hiroshi Iwai +6 more
TL;DR: In this article, the effect of upper-corner angle of trapezoidal and rectangular shape of silicon nanowire field effect transistors (SiNW FETs) on effective carrier mobility and normalized inversion charge density was investigated.
Journal ArticleDOI
Junctionless nanowire transistors operation at temperatures down to 4.2 K
Renan Trevisoli,Michelly de Souza,Rodrigo T. Doria,Valeriya Kilchtyska,Denis Flandre,Marcelo Antonio Pavanello +5 more
TL;DR: In this paper, the drain current, the transconductance, output conductance, the subthreshold slope, the threshold voltage and the interface trap density are the key parameters under analysis.
Journal ArticleDOI
Negative-Bias Temperature Instability in Gate-All-Around Silicon Nanowire MOSFETs: Characteristic Modeling and the Impact on Circuit Aging
Changze Liu,Tao Yu,Runsheng Wang,Liangliang Zhang,Ru Huang,Dong-Won Kim,Donggun Park,Yangyuan Wang +7 more
TL;DR: In this paper, the negative bias temperature instability (NBTI) in p-type gate-all-around silicon nanowire MOSFETs is investigated for circuit aging analysis.
Journal ArticleDOI
Compact Modeling of Cross-Sectional Scaling in Gate-All-Around FETs: 3-D to 1-D Transition
TL;DR: This is the first compact model capturing cross-sectional size-dependent dimensional crossover (3-D to 1-D) in , and provides a compact model for VLSI circuit simulation, especially for analog and RF circuits that will be seriously affected by the new humps and peaks introduced by the subbands.
Journal ArticleDOI
High-Performance Si Nanowire Transistors on Fully Si Bulk Substrate From Top-Down Approach: Simulation and Fabrication
Jing Zhuge,Yu Tian,Runsheng Wang,Ru Huang,Yiqun Wang,Baoqin Chen,Jia Liu,Xing Zhang,Yangyuan Wang +8 more
TL;DR: In this paper, a new method to fabricate high-performance gate-all-around silicon (Si) nanowire transistors (SNWTs) based on fully Si bulk (FSB) substrate is proposed and demonstrated by both simulation and experiments.
References
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TL;DR: In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.
Journal ArticleDOI
Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's
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TL;DR: In this paper, a scaling theory for fully-depleted, cylindrical MOSFET's was presented. But the scaling theory was derived from the cylinrical form of Poisson's equation by assuming a parabolic potential in the radial direction.
Journal ArticleDOI
Multiple-gate SOI MOSFETs: device design guidelines
TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
Journal ArticleDOI
Integrated nanoscale electronics and optoelectronics: Exploring nanoscale science and technology through semiconductor nanowires*
Yu Huang,Charles M. Lieber +1 more
TL;DR: In this paper, a general approach for the synthesis of a broad range of semiconductor nanowires (NWs) with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism was introduced.