Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance
01 Dec 2006-pp 1-4
TL;DR: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.
Abstract: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well
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Journal Article•
27 Dec 2010-World Academy of Science, Engineering and Technology, International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering
TL;DR: In this paper, a vertical wire NMOS device fabricated using CMOS compatible processes is presented, where the impact of temperature on various device parameters is investigated in view of usual increase in surrounding temperature with device density.
Abstract: In this paper, we present a vertical wire NMOS device fabricated using CMOS compatible processes. The impact of temperature on various device parameters is investigated in view of usual increase in surrounding temperature with device density. Keywords—Gate-all-around, temperature dependence, silicon nanowire
9 citations
Cites background from "Ultra-Narrow Silicon Nanowire Gate-..."
...37mV/K reported in [6] for (a) (b) (c) World Academy of Science, Engineering and Technology International Journal of Electronics and Communication Engineering Vol:4, No:12, 2010...
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Dissertation•
01 Jan 2010
TL;DR: Hoyt et al. as mentioned in this paper investigated the hole mobility of gate-all-around nanowire MOSFETs with a conformal high-κ/metal gate process.
Abstract: Scaling MOSFETs beyond 15 nm gate lengths is extremely challenging using a planar device architecture due to the stringent criteria required for the transistor switching. The top-down fabricated, gate-all-around architecture with a Si nanowire channel is a promising candidate for future technology generations. The gate-all-around geometry enhances the electrostatic control and hence gate length scalability. In addition, it enables use of an undoped channel, which has the potential to minimize threshold voltage variation due to reduced random dopant fluctuations. However, there is little known about carrier mobility in Si nanowire MOSFETs. Because of the different crystal surface orientations, the nanowire sidewalls are expected to influence carrier transport. In addition, sidewall roughness due to non-ideal lithography and etch processes can degrade the carrier transport. Technological performance boosters are thus required to enhance electron and hole transport. Uniaxial strain engineering and maskless hydrogen thermal annealing are investigated in this thesis to enhance carrier mobility in gate-all-around nanowire MOSFETs. Uniaxial tensile stress of about 2 GPa was incorporated for the first time into suspended Si nanowire channels by a novel lateral relaxation and suspension technique. Gate-all-around strained-Si nanowire nMOSFETs were fabricated with nanowire widths in the range of 8 to 50 nm and 8 nm body thickness, demonstrating near ideal sub-threshold swing and an enhancement in long-channel current drive and transconductance of approximately 2X for strained-Si nanowires compared to control Si nanowires. Lowfield effective mobility of these devices was extracted using split capacitance-voltage measurements and the two-FET method. The analysis indicates electron mobility enhancement for strained-Si nanowires over their unstrained Si counterparts, as well as over planar SOI, specifically at high inversion charge densities. However, the mobility of these nanowires was shown to decrease with decreasing nanowire width, consistent with reported data on unstrained Si nanowires. A simple analytical model was developed to investigate the contribution of the sidewalls to the nanowire width dependence of the electron mobility. A new design and process technology was developed to accurately investigate the hole mobility of gate-allaround Si nanowires. A conformal high-κ/metal gate process, enabling uniform gating of the nanowire perimeter, was combined with a maskless hydrogen thermal anneal to reduce sidewall roughness scattering. Using this optimized process, long-channel devices with ideal sub-threshold swing (~60 mV/dec) and enhanced current drive were demonstrated, indicating the excellent quality of the nanowire/high-κ interface and low-roughness sidewalls. Capacitance-voltage characteristics of sub-micron-long Si nanowires were accurately measured and verified by quantum-mechanical simulations. Increased effective hole mobility with decreasing nanowire width was observed down to 12 nm for hydrogen annealed nanowires, attributed to the smooth, high-mobility non-(100) sidewalls. Thesis Supervisor: Judy L. Hoyt Title: Professor of Electrical Engineering
9 citations
TL;DR: In this article, a method based on light scattering intensity and ensemble electron microcopy (EM) measurements was proposed to determine the diameter of silicon nanowires (SiNWs) within a few nanometers (4.8 nm).
Abstract: Silicon nanowires (SiNWs) are an important class of materials for biomedical and electronics applications, with the nanowire diameter playing a fundamental role in device functionality. Here we present a method, based on light scattering intensity and ensemble electron microcopy (EM) measurements, that allows for a precise optical determination of a specific NW’s diameter within an accuracy of a few nanometers (4.8 nm), an error of only ∼8.0%. This method takes advantage of the strong dependence of optical scattering on SiNW diameter to construct an optical to EM transform, with Lorentz-Mie theory showing that this method can be used for NWs up to ∼150 nm in diameter. Additionally, this technique offers some potential insights into biophysical interactions, allowing the optical calibration of individual intracellular SiNW force probes, enabling a ∼100-fold improvement in experimental uncertainty. Using these probes, we were able to measure drug-induced vasoconstriction in human aortic smooth muscle cells ...
9 citations
TL;DR: In this paper, an optimized design for Si-nanowire FETs in terms of spacer dielectric constant (κsp), extension length (LEXT), nanowire diameter (Dnw), and operation voltage (VDD) was proposed for the sub-10 nm technology node.
Abstract: In this paper, we propose an optimized design for Si-nanowire FETs in terms of spacer dielectric constant (κsp), extension length (LEXT), nanowire diameter (Dnw), and operation voltage (VDD) for the sub-10 nm technology node. Using well-calibrated TCAD simulations and analytic RC models, we have quantitatively evaluated geometry-dependent parasitic series resistances (RSD) and capacitances (Cpara). Compared with low-κ spacers, high-κ spacers exhibit a higher on/off-current ratio with a lower RSD, but show severe degradation in their AC performance owing to a higher Cpara. Considering the trade-off between RSD and Cpara, optimal geometry-dependent κsp values at various supply voltages (VDD) are determined using gate delay (CV/I) and current-gain cutoff frequency (fT). We found that as LEXT and VDD decrease and Dnw increases, the optimal κsp value shifts from the high-κ to low-κ regime.
9 citations
TL;DR: In this article, the impact of gate dielectric geometry on gate tunneling in a cylindrical-gate nanowire (NW) transistor was investigated and an analytical 2-D gate-tuning model was developed and used to assess quantitatively the tunneling probability in the CG NW transistor.
Abstract: In this letter, we report for the first time the impact of gate dielectric geometry on gate tunneling in a cylindrical-gate (CG) nanowire (NW) transistor. An analytical 2-D gate tunneling model is developed and used to assess quantitatively the tunneling probability in the CG NW transistor. A reduction in gate tunneling probability is predicted in the CG NW transistor compared with a planar-gate (PG) transistor with the same dielectric thickness. This effect can be very significant when the dielectric curvature is large as in practical NW devices. A high- k gate dielectric is more effective in suppressing the gate tunneling in CG transistors than in PG transistors.
8 citations
References
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TL;DR: In this article, a review highlights the recent advances in the field, using work from this laboratory for illustration, and the understanding of general nanocrystal growth mechanisms serves as the foundation for the rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks.
Abstract: ▪ Abstract Semiconductor nanowires and nanotubes exhibit novel electronic and optical properties owing to their unique structural one-dimensionality and possible quantum confinement effects in two dimensions. With a broad selection of compositions and band structures, these one-dimensional semiconductor nanostructures are considered to be the critical components in a wide range of potential nanoscale device applications. To fully exploit these one-dimensional nanostructures, current research has focused on rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks, and integration of nanowire elements into complex functional architectures. Significant progress has been made in a few short years. This review highlights the recent advances in the field, using work from this laboratory for illustration. The understanding of general nanocrystal growth mechanisms serves as the foundation for the rational sy...
1,407 citations
TL;DR: In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.
Abstract: This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.
605 citations
TL;DR: In this paper, a scaling theory for fully-depleted, cylindrical MOSFET's was presented. But the scaling theory was derived from the cylinrical form of Poisson's equation by assuming a parabolic potential in the radial direction.
Abstract: We present a scaling theory for fully-depleted, cylindrical MOSFET's. This theory was derived from the cylindrical form of Poisson's equation by assuming a parabolic potential in the radial direction. Numerical device simulation data for subthreshold slope and DIBL were compared to the model to validate the formula. By employing the scaling theory a comparison with double-gate (DG) MOSFET's was carried out illustrating an improvement of up to 40% in the minimum effective channel length for the cylindrical device.
551 citations
TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
Abstract: This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.
477 citations
TL;DR: In this paper, a general approach for the synthesis of a broad range of semiconductor nanowires (NWs) with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism was introduced.
Abstract: Semiconductor nanowires (NWs) represent an ideal system for investigating low- dimensional physics and are expected to play an important role as both interconnects and functional device elements in nanoscale electronic and optoelectronic devices Here we re- view a series of key advances defining a new paradigm of bottom-up assembling integrated nanosystems using semiconductor NW building blocks We first introduce a general ap- proach for the synthesis of a broad range of semiconductor NWs with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism Subsequently, we describe rational strategies for the hierarchical assembly of NW building blocks into functional devices and complex architectures based on electric field or micro-fluidic flow Next, we discuss a vari- ety of new nanoscale electronic device concepts including crossed NW p-n diode and crossed NW field effect transistors (FETs) Reproducible assembly of these scalable crossed NW de- vice elements enables a catalog of integrated structures, including logic gates and computa- tional circuits Lastly, we describe a wide range of photonic and optoelectronic devices, in- cluding nanoscale light-emitting diodes (nanoLEDs), multicolor LED arrays, integrated nanoLED-nanoFET arrays, single nanowire waveguide, and single nanowire nanolaser The potential application of these nanoscale light sources for chemical and biological analyses is discussed
252 citations