Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance
01 Dec 2006-pp 1-4
TL;DR: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.
Abstract: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well
Citations
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01 Jan 2013
TL;DR: A significant approach to enhance information throughput beyond the traditional scaling is to integrate the best features of the current memories into a fabrication technology compatible with CMOS technology process with better scalability than SRAM and FLASH.
Abstract: A significant approach to enhance information throughput beyond the traditional scaling is to integrate the best features of the current memories into a fabrication technology compatible with CMOS technology process with better scalability than SRAM and FLASH [1]. The fabrication technology should be applicable to both stand-alone and embedded memory applications. A major detractor of MPU ability to execute programs is the time delay needed for transferring data between the processor and memory. Such a fabrication technology can increase MPU cache memory which yields a much faster data processing. Furthermore, the development of high speed and high density random access nonvolatile memory is a great success in computer architecture.
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TL;DR: The results show that the extension length-tuned access transistor is an excellent option for improving the satiability with low power for sub-14-nm technologies.
7Â citations
19 Mar 2012
TL;DR: An electro-thermal model is proposed for the first time to accurately investigate the self-heating effects in gate-all-around (GAA) silicon nanowire MOSFETs (SNWTs) for thermal-aware design optimization.
Abstract: In this paper, an electro-thermal model is proposed for the first time to accurately investigate the self-heating effects in gate-all-around (GAA) silicon nanowire MOSFETs (SNWTs) for thermal-aware design optimization. The model is derived based on the equivalent thermal network method, in which the impacts of gate length dependence, nanowire diameter dependence and surface roughness on the nanowire channel thermal conductivity as well as the influence of unique GAA structure features on the heat dissipation are taken into account. The proposed model agrees well with the experimental results of SNWTs. Based on the model, the impacts of structure parameters on the current driving capabilities and heat dissipation of SNWTs are discussed. The developed electro-thermal model can be further applied to the thermal-aware design of SNWT-based circuits.
6Â citations
03 Apr 2009
TL;DR: In this paper, the impact of surface and transport, orientation on hole transport in p-type silicon nanowire MOSFET has been studied using atomistic 10-band sp3s*-SO tight-binding valence band model along with semi classical ballistic top-of-the-barrier approach for tri-gated devices.
Abstract: Impact of surface and transport, orientation on hole transport in p-type silicon nanowire MOSFET has been studied using atomistic 10-band sp3s*-SO tight-binding valence band model along with semi classical ballistic top-of-the-barrier approach for tri-gated devices. (100) and (110) surface orientations for and transport orientations were studied. Study of channel current and charge show that, due to heavy hole mass anisotropy, different confinement surfaces impact device performance differently. Keywords-component; nanowire, p-mos, top-of-the-barrier, tight binding, holes, valence-bands, transistor, injection-velocity, anisotropy
6Â citations
TL;DR: In this paper, the influence of bending on silicon nanowires of 1 nm to 4.3 nm diameter was investigated using molecular dynamics and quantum transport simulations, and the effect of bending strain and nanowire diameter on electronic transport and the transmission energy gap was analyzed.
Abstract: Moderate amount of bending strains, ~3% are enough to induce the semiconductor-metal transition in Si nanowires of ~4nm diameter. The influence of bending on silicon nanowires of 1 nm to 4.3 nm diameter is investigated using molecular dynamics and quantum transport simulations. Local strains in nanowires are analyzed along with the effect of bending strain and nanowire diameter on electronic transport and the transmission energy gap. Interestingly, relatively wider nanowires are found to undergo semiconductor-metal transition at relatively lower bending strains. The effect of bending strain on electronic properties is then compared with the conventional way of straining, i.e. uniaxial, which shows that, the bending is much more efficient way of straining to enhance the electronic transport and also to induce the semiconductor-metal transition in experimentally realizable Si nanowires.
6Â citations
References
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TL;DR: In this article, a review highlights the recent advances in the field, using work from this laboratory for illustration, and the understanding of general nanocrystal growth mechanisms serves as the foundation for the rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks.
Abstract: â–ª Abstract Semiconductor nanowires and nanotubes exhibit novel electronic and optical properties owing to their unique structural one-dimensionality and possible quantum confinement effects in two dimensions. With a broad selection of compositions and band structures, these one-dimensional semiconductor nanostructures are considered to be the critical components in a wide range of potential nanoscale device applications. To fully exploit these one-dimensional nanostructures, current research has focused on rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks, and integration of nanowire elements into complex functional architectures. Significant progress has been made in a few short years. This review highlights the recent advances in the field, using work from this laboratory for illustration. The understanding of general nanocrystal growth mechanisms serves as the foundation for the rational sy...
1,407Â citations
TL;DR: In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.
Abstract: This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.
605Â citations
TL;DR: In this paper, a scaling theory for fully-depleted, cylindrical MOSFET's was presented. But the scaling theory was derived from the cylinrical form of Poisson's equation by assuming a parabolic potential in the radial direction.
Abstract: We present a scaling theory for fully-depleted, cylindrical MOSFET's. This theory was derived from the cylindrical form of Poisson's equation by assuming a parabolic potential in the radial direction. Numerical device simulation data for subthreshold slope and DIBL were compared to the model to validate the formula. By employing the scaling theory a comparison with double-gate (DG) MOSFET's was carried out illustrating an improvement of up to 40% in the minimum effective channel length for the cylindrical device.
551Â citations
TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
Abstract: This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.
477Â citations
TL;DR: In this paper, a general approach for the synthesis of a broad range of semiconductor nanowires (NWs) with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism was introduced.
Abstract: Semiconductor nanowires (NWs) represent an ideal system for investigating low- dimensional physics and are expected to play an important role as both interconnects and functional device elements in nanoscale electronic and optoelectronic devices Here we re- view a series of key advances defining a new paradigm of bottom-up assembling integrated nanosystems using semiconductor NW building blocks We first introduce a general ap- proach for the synthesis of a broad range of semiconductor NWs with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism Subsequently, we describe rational strategies for the hierarchical assembly of NW building blocks into functional devices and complex architectures based on electric field or micro-fluidic flow Next, we discuss a vari- ety of new nanoscale electronic device concepts including crossed NW p-n diode and crossed NW field effect transistors (FETs) Reproducible assembly of these scalable crossed NW de- vice elements enables a catalog of integrated structures, including logic gates and computa- tional circuits Lastly, we describe a wide range of photonic and optoelectronic devices, in- cluding nanoscale light-emitting diodes (nanoLEDs), multicolor LED arrays, integrated nanoLED-nanoFET arrays, single nanowire waveguide, and single nanowire nanolaser The potential application of these nanoscale light sources for chemical and biological analyses is discussed
252Â citations