Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance
01 Dec 2006-pp 1-4
TL;DR: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.
Abstract: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well
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TL;DR: In this paper, the authors investigated the scaling trends of FinFET architecture, with focus on Front-End-of-Line (FEOL) and Middle-of Line (MOL) device parameters, and concluded that the combined requirements of device electrostatics together with the demands on contact resistance presents a Contacted-Gate-Pitch (CGP) scaling limit for horizontal-transport FETs.
Abstract: Scaling trends of FinFET architecture, with focus on Front-End-of-Line (FEOL), and Middle-of-Line (MOL) device parameters, is systematically investigated. It is concluded that the combined requirements of device electrostatics together with the demands on contact resistance, presents a Contacted-Gate-Pitch (CGP) scaling limit for horizontal-transport FETs. FET drive is expected to significantly degrade below this CGP ~ 40 nm as a result. Good agreement between hardware data and TCAD simulations is achieved and employed to estimate the contact resistance values for aggressively scaled FinFETs. These observations show that FinFETs scaled below CGP of 40 nm will require the contact resistivity (ρ
C
) of ~8 × 10
-10
Ω-cm
2
, while fully ohmic contacts i.e., ρ
C
of ~1 × 10
-10
Ω-cm
2
will be required if FinFETs are to extend performance below CGP of 30 nm. Ultimately, transition to new device architectures in which contact area is independent of CGP and/or Fin-Pitch will be necessary.
118 citations
Cites background from "Ultra-Narrow Silicon Nanowire Gate-..."
...performance requirements if the proper channel dimension is chosen [38]–[40]....
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TL;DR: In this article, the authors investigated the transport properties of silicon- nanowire FETs by using two different approaches to the solution of the Boltzmann equation for the quasi-1-D electron gas, namely, the Monte Carlo method and a deterministic numerical solver.
Abstract: We investigate the transport properties of silicon- nanowire FETs by using two different approaches to the solution of the Boltzmann equation for the quasi-1-D electron gas, namely, the Monte Carlo method and a deterministic numerical solver. In both cases, we first solve the coupled Schrodinger-Poisson equations to extract the profiles of the 1-D subbands along the channel; next, the coupled multisubband Boltzmann equations are tackled with the two different procedures. A very good agreement is achieved between the two approaches to the transport problem in terms of mobility, drain-current, and internal physical quantities, such as carrier-distribution functions and average velocities. Some peculiar features of the low-field mobility as a function of the wire diameter and gate bias are discussed and justified based on the subband energy and wave-function behavior within the cylindrical geometry of the nanowire, as well as the heavy degeneracy of the electron gas at large gate biases.
96 citations
Patent•
IBM1
TL;DR: In this paper, a high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability.
Abstract: A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wrap-around gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.
96 citations
TL;DR: In this article, detailed physical mechanisms of gate-induced drain leakage (GIDL) in gate-all-around silicon nanowire transistors (SNWTs) are investigated and verified by experiments and TCAD studies.
Abstract: In this paper, detailed physical mechanisms of gate-induced drain leakage (GIDL) in gate-all-around silicon nanowire transistors (SNWTs) are investigated and verified by experiments and TCAD studies. The results show that the SNWTs will suffer from a more severe GIDL issue in small diameter ( $D_{\rm nw}$ ) devices under low $|V_{\rm gs}|$ . It is believed that this unexpected GIDL problem in SNWTs origins from the longitudinal band-to-band tunneling (L-BTBT) at the body/drain junction enhanced by the strong gate coupling to the depletion region, which usually can be neglected in planar devices. On the other hand, the traditional transverse BTBT (T-BTBT) only dominates at high $|V_{\rm gs}|$ with relatively large $D_{\rm nw}$ . Systematic study of GIDL dependence on process parameters, including $D_{\rm nw}$ cross-sectional shape, doping, and overlap length ( $L_{\rm ov}$ ), shows that both T-BTBT and L-BTBT can be alleviated by reducing the doping and rounding the corner, but L-BTBT is worsened by reducing $D_{\rm nw}$ and $L_{\rm ov}$ despite of the alleviated T-BTBT. As the extension process engineering strongly impacts the short-channel effect and driving current of SNWTs, a GIDL optimization strategy considering the leakage power and device performance is given for low-power SNWT design.
95 citations
TL;DR: In this article, an n-type gate-all-around (GAA) junctionless nanowire field effect transistor (JL-NWFET) along with low-frequency noise (LFN) with respect to channel doping and the gate bias voltage was presented.
Abstract: We present n-type gate-all-around (GAA) junctionless nanowire field-effect transistor (JL-NWFET) along with low-frequency noise (LFN) with respect to channel doping and the gate bias voltage. Irrespective of doping level in the channel, which is the same as that of source/drain, the JL-NWFET shows approximately five orders of magnitude lower spectral noise than the inversion-mode counterpart. LFN in JL-NWFET is also found less sensitive to gate bias voltage and to the frequency. The superior LFN behavior in GAA JL-NWFET is attributed to the conduction of carriers inside the uniformly doped nanowire channel. JL-NWFET-based sensing elements can thus be suitable in physical transducers to maximize the detection limits.
82 citations
Cites methods from "Ultra-Narrow Silicon Nanowire Gate-..."
...Inversion-mode GAA NWFETs were fabricated on separate wafers with the process flow described in previous work [ 11 ]....
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References
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TL;DR: In this article, a review highlights the recent advances in the field, using work from this laboratory for illustration, and the understanding of general nanocrystal growth mechanisms serves as the foundation for the rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks.
Abstract: ▪ Abstract Semiconductor nanowires and nanotubes exhibit novel electronic and optical properties owing to their unique structural one-dimensionality and possible quantum confinement effects in two dimensions. With a broad selection of compositions and band structures, these one-dimensional semiconductor nanostructures are considered to be the critical components in a wide range of potential nanoscale device applications. To fully exploit these one-dimensional nanostructures, current research has focused on rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks, and integration of nanowire elements into complex functional architectures. Significant progress has been made in a few short years. This review highlights the recent advances in the field, using work from this laboratory for illustration. The understanding of general nanocrystal growth mechanisms serves as the foundation for the rational sy...
1,407 citations
TL;DR: In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.
Abstract: This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.
605 citations
TL;DR: In this paper, a scaling theory for fully-depleted, cylindrical MOSFET's was presented. But the scaling theory was derived from the cylinrical form of Poisson's equation by assuming a parabolic potential in the radial direction.
Abstract: We present a scaling theory for fully-depleted, cylindrical MOSFET's. This theory was derived from the cylindrical form of Poisson's equation by assuming a parabolic potential in the radial direction. Numerical device simulation data for subthreshold slope and DIBL were compared to the model to validate the formula. By employing the scaling theory a comparison with double-gate (DG) MOSFET's was carried out illustrating an improvement of up to 40% in the minimum effective channel length for the cylindrical device.
551 citations
TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
Abstract: This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.
477 citations
TL;DR: In this paper, a general approach for the synthesis of a broad range of semiconductor nanowires (NWs) with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism was introduced.
Abstract: Semiconductor nanowires (NWs) represent an ideal system for investigating low- dimensional physics and are expected to play an important role as both interconnects and functional device elements in nanoscale electronic and optoelectronic devices Here we re- view a series of key advances defining a new paradigm of bottom-up assembling integrated nanosystems using semiconductor NW building blocks We first introduce a general ap- proach for the synthesis of a broad range of semiconductor NWs with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism Subsequently, we describe rational strategies for the hierarchical assembly of NW building blocks into functional devices and complex architectures based on electric field or micro-fluidic flow Next, we discuss a vari- ety of new nanoscale electronic device concepts including crossed NW p-n diode and crossed NW field effect transistors (FETs) Reproducible assembly of these scalable crossed NW de- vice elements enables a catalog of integrated structures, including logic gates and computa- tional circuits Lastly, we describe a wide range of photonic and optoelectronic devices, in- cluding nanoscale light-emitting diodes (nanoLEDs), multicolor LED arrays, integrated nanoLED-nanoFET arrays, single nanowire waveguide, and single nanowire nanolaser The potential application of these nanoscale light sources for chemical and biological analyses is discussed
252 citations