Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance
01 Dec 2006-pp 1-4
TL;DR: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.
Abstract: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well
Citations
More filters
06 Oct 2011
TL;DR: In this article, a method to couple the sp3d5s*-spin-orbit-coupled (SO) atomistic tight-binding model and linearized Boltzmann transport theory for the calculation of low-field mobility in Si nanowires (NWs) is described.
Abstract: We describe a method to couple the sp3d5s*-spin-orbit-coupled (SO) atomistic tight-binding (TB) model and linearized Boltzmann transport theory for the calculation of low-field mobility in Si nanowires (NWs). We consider scattering mechanisms due to phonons and surface roughness. We perform a simulation study of the low-field mobility in n-type and p-type Si NWs of diameters from 3nm to 12nm, in the [100], [110] and [111] transport orientations. We find that the NW mobility is a strong function of orientation and diameter. This is a consequence of the large variations in the electronic structure with geometry and quantization. Especially in the case of p-type [111] and [110] NWs, large phonon-limited mobility improvements with diameter scaling are observed.
2 citations
Cites background from "Ultra-Narrow Silicon Nanowire Gate-..."
...NW devices with channels of just a few nanometers in diameter have already been demonstrated [2, 3, 4, 5]....
[...]
TL;DR: In this article, the degradation of 1/f noise levels that is caused by Fowler-Nordheim (FN) tunneling stress for both the silicon nanowire transistor (SNWT) and the FinFET was investigated.
Abstract: The purpose of this brief is to investigate the degradation of 1/f noise levels that is caused by Fowler-Nordheim (FN) tunneling stress for both the silicon nanowire transistor (SNWT) and the FinFET. The oxide traps that are generated under constant-voltage FN stress are extracted from the 1/f noise characteristics. Under the same FN stress voltage and time, the amount of oxide traps that is generated in the cylindrical-channel SNWT is much larger than that generated in the planar-channel FinFET, which is due to the increased electric field at the SiO2/Si interface that is caused by the cylindrical architecture of the SNWT.
2 citations
Cites background from "Ultra-Narrow Silicon Nanowire Gate-..."
...gate-all-around (GAA) silicon nanowire transistor (SNWT), is considered an important candidate for future CMOS scaling beyond the 32-nm node [1]–[3]....
[...]
...ones reported earlier in [3] and [8], respectively....
[...]
Dissertation•
01 Jan 2014
2 citations
Cites background or methods or result from "Ultra-Narrow Silicon Nanowire Gate-..."
...The QCSE can be minimized by orienting heterojunctions along nonpolar orientations orthogonal to the c-direction, including the [11-20] a-direction and [1-100] m-direction (Figure 2-7c)....
[...]
...The majority of nanowires grew in the [1-100] m-direction on a-GaN substrates, while the majority grew in the [0001] c-direction on c-GaN substrates, similar to the results for GaN nanowires....
[...]
...In nanowires, this can be achieved by fabricating radial heterojunctions around c-oriented nanowires or axial heterojunctions along nonpolar-oriented nanowires, including the [1-100] m-direction and the [11-20] a-direction, although other potential nonpolar orientations do exist....
[...]
...Both Au- and Ni-seeded nanowires grew preferentially in the [1-100] m-direction, as confirmed by selected area diffraction (SAD)....
[...]
...As with previous GaN studies, r-sapphire substrates coated with 1 nm Au films produced GaN nanowires orientated in the [1-100] m-...
[...]
TL;DR: It is found that for donors and acceptors, the DFT charge distribution extends similarly in both materials, and the relaxed structure produces a 50% larger spread of electronic charge as compared with unrelaxed Si and GaAs.
Abstract: In this work, electron densities around dopants in Si and GaAs have been calculated using density functional theory (DFT) calculations. These extracted densities have been used to describe dopants in an in-house non-equilibrium Green functions device simulator. The transfer characteristics of nanowire gate all around field effect transistor have been calculated using DFT electron densities. These transport calculations were compared with those using a point charge model of the dopant. The dopants are located in the middle of the channel of the device. Specifically, DFT calculations of a 512 atom Si supercell with a single impurity atom have been carried out, both phosphorous and boron atoms have been used as donor and acceptor impurities respectively. The calculations were repeated on a gallium arsenide supercell, where the silicon atom substituted gallium and arsenide to act as donor and acceptor respectively. We found that for donors and acceptors, the DFT charge distribution extends similarly in both materials. In addition, the relaxed structure produces a 50% larger spread of electronic charge as compared with unrelaxed Si and GaAs. The extracted current voltage characteristics of the devices are altered significantly using the charge density obtained by DFT. At 0.7 V the current in Si is 20% larger using the DFT charge density compared to the point charge model for donors. Whereas the current using the point charge model in GaAs is 2.5 times larger than the distributed charge. Devices exhibit substantial tunnelling currents for donors and acceptors irrespective of the model of the dopant considered. In GaAs, this was 76% using a point charge and 78% using the distributed charge when using a donor; 61% and 68% in Si respectively. The tunnelling current using acceptors for Si was 100% and 99% using GaAs for both models.
2 citations
Cites background from "Ultra-Narrow Silicon Nanowire Gate-..."
...Nanowires with various channel lengths and cross sections have been fabricated [3, 4, 5]....
[...]
TL;DR: In this paper, the authors demonstrate the low power functionality of silicon nanowire (SiNW)-assembled inverters on bendable plastics, which are capable of operating at supply voltages as low as 0.8 V with a switching (or standby) power consumption of ∼0.2 nW (or ∼6.6 pW).
Abstract: In this paper, we demonstrate the low-power functionality of silicon nanowire (SiNW)-assembled inverters on bendable plastics. Our bendable inverters are capable of operating at supply voltages as low as 0.8 V with a switching (or standby) power consumption of ∼0.2 nW (or ∼6.6 pW). The low-power inverting operation with a voltage gain of ∼18 is attributable to the near-ideal characteristics of the component transistors that have selectively thinned SiNW channels and exhibit low, symmetrical threshold voltages of 0.40 and −0.39 V and low sub-threshold swing values of 81 and 65 mV/dec. Moreover, mechanical bendability reveals that the inverting operation has good, stable fatigue properties.
2 citations
References
More filters
TL;DR: In this article, a review highlights the recent advances in the field, using work from this laboratory for illustration, and the understanding of general nanocrystal growth mechanisms serves as the foundation for the rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks.
Abstract: ▪ Abstract Semiconductor nanowires and nanotubes exhibit novel electronic and optical properties owing to their unique structural one-dimensionality and possible quantum confinement effects in two dimensions. With a broad selection of compositions and band structures, these one-dimensional semiconductor nanostructures are considered to be the critical components in a wide range of potential nanoscale device applications. To fully exploit these one-dimensional nanostructures, current research has focused on rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks, and integration of nanowire elements into complex functional architectures. Significant progress has been made in a few short years. This review highlights the recent advances in the field, using work from this laboratory for illustration. The understanding of general nanocrystal growth mechanisms serves as the foundation for the rational sy...
1,407 citations
TL;DR: In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.
Abstract: This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.
605 citations
TL;DR: In this paper, a scaling theory for fully-depleted, cylindrical MOSFET's was presented. But the scaling theory was derived from the cylinrical form of Poisson's equation by assuming a parabolic potential in the radial direction.
Abstract: We present a scaling theory for fully-depleted, cylindrical MOSFET's. This theory was derived from the cylindrical form of Poisson's equation by assuming a parabolic potential in the radial direction. Numerical device simulation data for subthreshold slope and DIBL were compared to the model to validate the formula. By employing the scaling theory a comparison with double-gate (DG) MOSFET's was carried out illustrating an improvement of up to 40% in the minimum effective channel length for the cylindrical device.
551 citations
TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
Abstract: This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.
477 citations
TL;DR: In this paper, a general approach for the synthesis of a broad range of semiconductor nanowires (NWs) with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism was introduced.
Abstract: Semiconductor nanowires (NWs) represent an ideal system for investigating low- dimensional physics and are expected to play an important role as both interconnects and functional device elements in nanoscale electronic and optoelectronic devices Here we re- view a series of key advances defining a new paradigm of bottom-up assembling integrated nanosystems using semiconductor NW building blocks We first introduce a general ap- proach for the synthesis of a broad range of semiconductor NWs with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism Subsequently, we describe rational strategies for the hierarchical assembly of NW building blocks into functional devices and complex architectures based on electric field or micro-fluidic flow Next, we discuss a vari- ety of new nanoscale electronic device concepts including crossed NW p-n diode and crossed NW field effect transistors (FETs) Reproducible assembly of these scalable crossed NW de- vice elements enables a catalog of integrated structures, including logic gates and computa- tional circuits Lastly, we describe a wide range of photonic and optoelectronic devices, in- cluding nanoscale light-emitting diodes (nanoLEDs), multicolor LED arrays, integrated nanoLED-nanoFET arrays, single nanowire waveguide, and single nanowire nanolaser The potential application of these nanoscale light sources for chemical and biological analyses is discussed
252 citations