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Proceedings ArticleDOI

Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance

TL;DR: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.
Abstract: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well
Citations
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Journal ArticleDOI
TL;DR: In this article, variable temperature charge transport measurements of tri-gate silicon-on-insulator MOSFETs with fin widths of 11-nm, fin heights of 58-nm and gate lengths ranging from 80-nm to 250-nm were reported.
Abstract: We report on variable temperature charge transport measurements of tri-gate silicon-on-insulator MOSFETs with fin widths of 11 nm, fin heights of 58 nm and gate lengths ranging from 80 nm to 250 nm. Reproducible inflection points were observed in drain current vs. gate voltage data acquired at low temperature (4–8 K) and low drain bias (0.1 mV), yielding oscillations in the extracted transconductance data which are consistent with formation of a one-dimensional electron gas in the channel. Simulations of the variation in fin potential with gate voltage indicate transport through ∼3 sub-bands per fin at gate overdrive of 100 mV above threshold. Observed multi-peak envelopes in measured transconductance vs. gate voltage data for multiple-fin devices suggest sub-band separations ∼20 mV, in reasonable agreement with simulation results (27–55 mV). The measured conductance per fin at low temperatures (4–6 K) was on the order of the quantum conductance, consistent with diffusive transport through multiple sub-bands. Measured transconductance features were largely reproducible for repeated measurements on a given device, although slight variations could be observed, possibly due to quantum interference or interface charges.

2 citations

Journal ArticleDOI
TL;DR: In this paper, a 20-band spin-orbit-coupled, semi-empirical, atomistic tight binding model is used with a semi-classical, ballistic, field effect transistor (FET) model, to examine the ON-current variations to size variations of [110] oriented PMOS nanowire devices.
Abstract: A 20-band sp3d5s* spin-orbit-coupled, semi-empirical, atomistic tight-binding model is used with a semi-classical, ballistic, field-effect-transistor (FET) model, to examine the ON-current variations to size variations of [110] oriented PMOS nanowire devices. Infinitely long, uniform, rectangular nanowires of side dimensions from 3nm to 12nm are examined and significantly different behavior in width vs. height variations are identified and explained. Design regions are identified, which show minor ON-current variations to significant width variations that might occur due to lack of line width control. Regions which show large ON-current variations to small height variations are also identified. The considerations of the full band model here show that ON-current doubling can be observed in the ON-state at the onset of volume inversion to surface inversion transport caused by structural side size variations. Strain engineering can smooth out or tune such sensitivities to size variations. The cause of variations described is the structural quantization behavior of the nanowires, which provide an additional variation mechanism to any other ON-current variations such as surface roughness, phonon scattering etc.

2 citations

Proceedings ArticleDOI
18 May 2012
TL;DR: In this paper, a three dimensional self-consistent Schrodinger- Poisson solver based on the semi-empirical tight binding method was used to optimize 10 nm gate Silicon Nanowire Field Effect Transistors.
Abstract: We utilize a three dimensional self-consistent Schrodinger- Poisson solver based on the semi-empirical tight binding method to optimize 10 nm gate Silicon Nanowire Field Effect Transistors. Parameters sensitive to the device performance such as diameter of nanowire, gate oxide thickness and crystal axis are chosen to be varied to tune the device performance. Small signal analysis has been performed and critical parameters such as threshold voltage, subthreshold swing and ON/OFF current ratio are calculated from the simulation data. Our simulation results show that quantum nature of transport dominates in the interesting regime and can significantly enhances device performance. Thus sensitivity of device performance to the process variation at room temperature has been explored to meet the fabrication challenge of Nanowire based transistors.

2 citations


Cites methods from "Ultra-Narrow Silicon Nanowire Gate-..."

  • ...Several groups have employed OMEN to investigate the effects of anisotropy of quantization mass [3], size variations, doping profile, interface roughness [4], crystal orientation and temperature dependence [5] on NW transport and FET modeling....

    [...]

Journal ArticleDOI
TL;DR: In this article, the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length was explored and the potential benefits of such a multigate structure for analog and RF design were evaluated in terms of intrinsic gain (AV), output conductance (gd), trans-conductance (gm), gate capacitance (Cgg), and cut-off frequency (fT = gm/2πCgg) with spacer regions variations.
Abstract: Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short channel effects (SCEs), leakage currents, device variability and reliability etc. Nowadays, multigate structure has become the promising candidate to overcome these problems. SOI FinFET is one of the best multigate structures that has gained importance in all electronic design automation (EDA) industries due to its improved short channel effects (SCEs), because of its more effective gate-controlling capabilities. In this paper, our aim is to explore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length. Electric field modulation is analyzed with spacer length variation and electrostatic performance is evaluated in terms of performance parameter like electron mobility, electric field, electric potential, sub-threshold slope (SS), ON current (Ion), OFF current (Ioff) and Ion/Ioff ratio. The potential benefits of SOI FinFET at drain-to-source voltage, VDS = 0.05 V and VDS = 0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain (AV), output conductance (gd), trans-conductance (gm), gate capacitance (Cgg), and cut-off frequency (fT = gm/2πCgg) with spacer region variations.

2 citations

Proceedings ArticleDOI
14 Oct 2019
TL;DR: In this article, a unified phenomenological model for insulator capacitance in rectangular (i.e., Nanosheet) cross-section gate-all-around (GAA) FET was developed to solve the gate charge density accurately.
Abstract: Lateral nanosheet field-effect-transistor (FET) is now targeting for 3nm CMOS technology node [1], [2]. It is important to see quantization effect at such confined geometry. In this work, we study the geometrical confinement effects in silicon nanosheet. We developed a unified phenomenological model for insulator capacitance (C ins ) in rectangular (i.e., Nanosheet) cross-section gate-all-around (GAA) FET to solve the gate charge density accurately. It is observed that multi-subband conduction causes humps in higher order derivatives of charge vs gate voltage characteristics which may affect the performance of analog and RF circuits.

2 citations

References
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Journal ArticleDOI
TL;DR: In this article, a review highlights the recent advances in the field, using work from this laboratory for illustration, and the understanding of general nanocrystal growth mechanisms serves as the foundation for the rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks.
Abstract: ▪ Abstract Semiconductor nanowires and nanotubes exhibit novel electronic and optical properties owing to their unique structural one-dimensionality and possible quantum confinement effects in two dimensions. With a broad selection of compositions and band structures, these one-dimensional semiconductor nanostructures are considered to be the critical components in a wide range of potential nanoscale device applications. To fully exploit these one-dimensional nanostructures, current research has focused on rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks, and integration of nanowire elements into complex functional architectures. Significant progress has been made in a few short years. This review highlights the recent advances in the field, using work from this laboratory for illustration. The understanding of general nanocrystal growth mechanisms serves as the foundation for the rational sy...

1,407 citations

Journal ArticleDOI
TL;DR: In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.
Abstract: This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.

605 citations

Journal ArticleDOI
TL;DR: In this paper, a scaling theory for fully-depleted, cylindrical MOSFET's was presented. But the scaling theory was derived from the cylinrical form of Poisson's equation by assuming a parabolic potential in the radial direction.
Abstract: We present a scaling theory for fully-depleted, cylindrical MOSFET's. This theory was derived from the cylindrical form of Poisson's equation by assuming a parabolic potential in the radial direction. Numerical device simulation data for subthreshold slope and DIBL were compared to the model to validate the formula. By employing the scaling theory a comparison with double-gate (DG) MOSFET's was carried out illustrating an improvement of up to 40% in the minimum effective channel length for the cylindrical device.

551 citations

Journal ArticleDOI
TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
Abstract: This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.

477 citations

Journal ArticleDOI
TL;DR: In this paper, a general approach for the synthesis of a broad range of semiconductor nanowires (NWs) with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism was introduced.
Abstract: Semiconductor nanowires (NWs) represent an ideal system for investigating low- dimensional physics and are expected to play an important role as both interconnects and functional device elements in nanoscale electronic and optoelectronic devices Here we re- view a series of key advances defining a new paradigm of bottom-up assembling integrated nanosystems using semiconductor NW building blocks We first introduce a general ap- proach for the synthesis of a broad range of semiconductor NWs with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism Subsequently, we describe rational strategies for the hierarchical assembly of NW building blocks into functional devices and complex architectures based on electric field or micro-fluidic flow Next, we discuss a vari- ety of new nanoscale electronic device concepts including crossed NW p-n diode and crossed NW field effect transistors (FETs) Reproducible assembly of these scalable crossed NW de- vice elements enables a catalog of integrated structures, including logic gates and computa- tional circuits Lastly, we describe a wide range of photonic and optoelectronic devices, in- cluding nanoscale light-emitting diodes (nanoLEDs), multicolor LED arrays, integrated nanoLED-nanoFET arrays, single nanowire waveguide, and single nanowire nanolaser The potential application of these nanoscale light sources for chemical and biological analyses is discussed

252 citations

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