Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance
01 Dec 2006-pp 1-4
TL;DR: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.
Abstract: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well
Citations
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TL;DR: Quasi-planar bulk Tr.
Abstract: We propose a low-cost and highly scalable embedded nonvolatile memory using a quasi-planar bulk transistor fabricated with a standard CMOS process. Program and erase operation was achieved by hot-electron injection into the gate dielectric and drain-assisted hot-hole injection and/or electron ejection, respectively. Thanks to the electric field concentration at the channel corners in quasi-planar bulk transistor, not only the program efficiency, but also the erase efficiency was enhanced with the decrease in channel width. Scaling of gate length also improved the program and erase characteristics. As a result, a threshold voltage window of more than 0.3 V was repeatedly attained. Moreover, 300 program and erase cycles and 10-year data retention were experimentally demonstrated. Thus, quasi-planar bulk Tr. memory was found to be highly suitable for nonvolatile memory embedded with low-power scaled CMOS.
1 citations
Patent•
13 Jul 2010
TL;DR: In this paper, a Gate-Elektrodenstapel is described as a material, e.g., a gate-elektronisches Bauelement, which is used to construct a leitenden Kanal, eine Kristallstruktur definiert und eine Lange and eine Dicke t c aufweist.
Abstract: Es wird ein elektronisches Bauelement beschrieben, das einen leitenden Kanal, der eine Kristallstruktur definiert und eine Lange und eine Dicke t C aufweist, und einen Gate-Elektrodenstapel der Dicke t g beinhaltet, der sich in Kontakt mit einer Flache des Kanals befindet. Ferner umfasst der Gate-Elektrodenstapel ein Material, das auf die Kontaktflache des Kanals eine Druckkraft oder eine Zugkraft derart ausubt, dass die elektrische Beweglichkeit der Ladungstrager (Elektronen oder Locher) uber die Lange des Kanals hinweg aufgrund der Druckkraft oder der Zugkraft in Abhangigkeit von der Ausrichtung der Langsachse des Kanals in Bezug auf die Kristallstruktur erhoht wird. Es werden Ausfuhrungsarten fur Chips, bei denen die Beweglichkeit sowohl der Locher als auch der Elektronen in verschiedenen Transistoren erhoht wird, sowie ein Verfahren zum Herstellen eines solchen Transistors oder Chips angegeben.
1 citations
01 Sep 2013
TL;DR: In this article, the bandstructure of p-type gated Si nanowires (NWs) is calculated self-consistently using the sp3d5s* atomistic tight-binding (TB) model and the 2D Poisson equation.
Abstract: The bandstructure of p-type gated Si nanowires (NWs) is calculated self-consistently using the sp3d5s* atomistic tight-binding (TB) model and the 2D Poisson equation. The Boltzmann transport formalism is then used for calculation of the low-field mobility. We show that the bandstructures of NWs in the [110] and [111] transport orientations change as the channel is driven into inversion, which causes a ~50% increase in their intrinsic phonon-limited hole mobility. For short channel MOSFET devices, however, the total mobility is lower that the intrinsic mobility because it is affected by the so-called “ballistic” mobility.
1 citations
Cites background from "Ultra-Narrow Silicon Nanowire Gate-..."
...Specifically for ultra-narrow ptype NWs, studies have shown that the carrier velocities and mobilities largely increase as the diameter is reduced down to D=3nm [7, 8, 9]....
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...Ultra-scaled NW devices of channel diameters down to D=3nm and lengths as short as 15nm with excellent performance have already been demonstrated by various experimental groups [2, 3, 4, 5]....
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TL;DR: In this article, a perfect temperature-dependent model for silicon nanowires including self-heating effects has been derived and its effects on device parameters have been observed, and significant reduction in noise with respect to channel thermal resistance, gate length, and biasing is analyzed.
Abstract: Silicon nanowires are leading the CMOS era towards the downsizing limit and its nature will be effectively suppress the short channel effects. Accurate modeling of thermal noise in nanowires is crucial for RF applications of nano-CMOS emerging technologies. In this work, a perfect temperature-dependent model for silicon nanowires including the self-heating effects has been derived and its effects on device parameters have been observed. The power spectral density as a function of thermal resistance shows significant improvement as the channel length decreases. The effects of thermal noise including self-heating of the device are explored. Moreover, significant reduction in noise with respect to channel thermal resistance, gate length, and biasing is analyzed.
1 citations
Dissertation•
01 Apr 2016
TL;DR: In this article, the photoresponse of nanowires with asymmetric contacts and bending strain was modeled and characterized using a photoregressive model and a bending strain model.
Abstract: Modeling and characterization of photoresponse of nanowires with asymmetric contacts and bending strain
1 citations
Cites background from "Ultra-Narrow Silicon Nanowire Gate-..."
...nanotransistors [60], [61], [125], solar cells [1], [3], [11]), optoelectronic devices [126], sensors [62], [63], [127], [128], as well as thermoelectric energy conversions [129], [130]....
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References
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TL;DR: In this article, a review highlights the recent advances in the field, using work from this laboratory for illustration, and the understanding of general nanocrystal growth mechanisms serves as the foundation for the rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks.
Abstract: ▪ Abstract Semiconductor nanowires and nanotubes exhibit novel electronic and optical properties owing to their unique structural one-dimensionality and possible quantum confinement effects in two dimensions. With a broad selection of compositions and band structures, these one-dimensional semiconductor nanostructures are considered to be the critical components in a wide range of potential nanoscale device applications. To fully exploit these one-dimensional nanostructures, current research has focused on rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks, and integration of nanowire elements into complex functional architectures. Significant progress has been made in a few short years. This review highlights the recent advances in the field, using work from this laboratory for illustration. The understanding of general nanocrystal growth mechanisms serves as the foundation for the rational sy...
1,407 citations
TL;DR: In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.
Abstract: This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.
605 citations
TL;DR: In this paper, a scaling theory for fully-depleted, cylindrical MOSFET's was presented. But the scaling theory was derived from the cylinrical form of Poisson's equation by assuming a parabolic potential in the radial direction.
Abstract: We present a scaling theory for fully-depleted, cylindrical MOSFET's. This theory was derived from the cylindrical form of Poisson's equation by assuming a parabolic potential in the radial direction. Numerical device simulation data for subthreshold slope and DIBL were compared to the model to validate the formula. By employing the scaling theory a comparison with double-gate (DG) MOSFET's was carried out illustrating an improvement of up to 40% in the minimum effective channel length for the cylindrical device.
551 citations
TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
Abstract: This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.
477 citations
TL;DR: In this paper, a general approach for the synthesis of a broad range of semiconductor nanowires (NWs) with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism was introduced.
Abstract: Semiconductor nanowires (NWs) represent an ideal system for investigating low- dimensional physics and are expected to play an important role as both interconnects and functional device elements in nanoscale electronic and optoelectronic devices Here we re- view a series of key advances defining a new paradigm of bottom-up assembling integrated nanosystems using semiconductor NW building blocks We first introduce a general ap- proach for the synthesis of a broad range of semiconductor NWs with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism Subsequently, we describe rational strategies for the hierarchical assembly of NW building blocks into functional devices and complex architectures based on electric field or micro-fluidic flow Next, we discuss a vari- ety of new nanoscale electronic device concepts including crossed NW p-n diode and crossed NW field effect transistors (FETs) Reproducible assembly of these scalable crossed NW de- vice elements enables a catalog of integrated structures, including logic gates and computa- tional circuits Lastly, we describe a wide range of photonic and optoelectronic devices, in- cluding nanoscale light-emitting diodes (nanoLEDs), multicolor LED arrays, integrated nanoLED-nanoFET arrays, single nanowire waveguide, and single nanowire nanolaser The potential application of these nanoscale light sources for chemical and biological analyses is discussed
252 citations