Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance
01 Dec 2006-pp 1-4
TL;DR: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.
Abstract: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well
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TL;DR: In this article, the integration of gate-all-around (GAA) Si-nanowire transistors into CMOS inverters using top-down approach is demonstrated, for the first time, and the results are discussed in light of the circuit performances reported for other advanced nonclassical device architectures such as FinFETs.
Abstract: This letter demonstrates, for the first time, the integration of gate-all-around (GAA) Si-nanowire transistors into CMOS inverters using top-down approach. With matching of the drive currents of n- and p-MOSFETs using different gate lengths to achieve symmetric pull-up and pull-down, sharp ON- OFF transitions with high voltage gains (e.g., DeltaV OUT/DeltaV IN up to ~ 40 for V DD = 1.2 V) are obtained. The inverter maintains its good transfer characteristics and noise margins for wide range of V DD tested down to 0.4 V. Individual transistors show excellent subthreshold characteristics and drive currents. The results are discussed in light of the circuit performances reported for other advanced nonclassical device architectures such as FinFETs. The integration potential of GAA Si-nanowire transistors to realize CMOS-circuit functionality is thus demonstrated.
79 citations
TL;DR: In this paper, a gate-all-around Si-nanowire (NW) nonvolatile memory cell is proposed for high-speed NAND-type non-volatile flash memory applications.
Abstract: This letter presents a high-speed silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory cell in gate-all-around Si-nanowire (NW) architecture, which is fabricated by using a top-down process technology. The NW cell exhibits faster program and erase (P/E) speed compared to the corresponding planar device; 1 mus for programming and 1 ms for erasing at VGS = plusmn11 V with a threshold voltage shift "DeltaVTH" of 2.6 V using the Fowler-Nordheim tunneling mechanism. At these P/E conditions, the planar device does not show appreciable change. The improvement is originated from: 1) increased electric field at the Si-SiO2 interface; 2) reduced effective tunnel barrier width; and 3) low electric field in the blocking oxide, as analyzed through simulation. In addition, good data retention makes the NW-based SONOS cell a potential candidate for future high-speed low-voltage NAND-type nonvolatile Flash memory applications.
74 citations
Cites methods from "Ultra-Narrow Silicon Nanowire Gate-..."
...The process flow of Si-NW SONOS is similar to the previously reported NW-FETs with respect to the NW formation [8]....
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TL;DR: In this paper, the effect of random discrete dopants on the statistical variability in gate-all-around silicon nanowire transistors has been investigated using the nonequilibrium Green's function formalism.
Abstract: In this paper, we review and extend recent work on the effect of random discrete dopants on the statistical variability in gate-all-around silicon nanowire transistors. The electron transport is described using the nonequilibrium Green's function formalism. Full 3-D real-space and coupled-mode-space repre sentations are used. Two different cross sections (i.e., 2.2 × 2.2 and 4.2 × 4.2 nm2) and two different channel lengths (i.e., 6 and 12 nm) have been considered. The resistivity associated with discrete dopants can be estimated from the averaged current-voltage characteristics. The threshold-voltage variability and the sub threshold-slope variability are reduced greatly in the transistors with longer channel length. Both are smaller at equivalent channel lengths in the 2.2 × 2.2 nm2 device due to better electrostatic integrity. At the same time, the ON-state-current variability associated with the varying resistance of the access regions is virtually independent of the channel length. However, it is reduced greatly in the 4.2 × 4.2 nm2 transistor due to a fourfold increase in the number of dopants in the access regions and corresponding self-averaging effects. Finally, we present results for the smallest transistor combining two sources of variability (i.e., discrete random dopants and surface roughness) and phonon scattering.
72 citations
Cites background from "Ultra-Narrow Silicon Nanowire Gate-..."
...2157929 MOSFETs to a channel length of sub-10 nm favor research into new device architectures such as silicon-on-insulator, finshaped FETs (FinFETs), and nanowire MOSFETs [1]....
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...Digital Object Identifier 10.1109/TED.2011.2157929 MOSFETs to a channel length of sub-10 nm favor research into new device architectures such as silicon-on-insulator, finshaped FETs (FinFETs), and nanowire MOSFETs [1]....
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TL;DR: In this paper, the influence of interface roughness scattering (IRS) on the performances of silicon nanowire (NW) field effect transistors is numerically investigated using a full 3D quantum transport simulator based on an atomistic sp3d5s* tight-binding model.
Abstract: The influence of interface roughness scattering (IRS) on the performances of silicon nanowire (NW) field-effect transistors is numerically investigated using a full 3-D quantum transport simulator based on an atomistic sp3d5s* tight-binding model. An interface between silicon and silicon dioxide layers is generated in a real-space atomistic representation using an experimentally derived autocovariance function. An oxide layer is modeled in a virtual crystal approximation using fictitious SiO2 atoms. 〈110〉-oriented NWs with different diameters and randomly generated surface configurations are studied. An experimentally observed on-current and threshold voltage are quantitatively captured by the simulation model. The mobility reduction due to IRS is studied through a qualitative comparison of the simulation results with the experimental data.
65 citations
Cites background from "Ultra-Narrow Silicon Nanowire Gate-..."
...[3]–[5], particularly in a gate-all-around (GAA) configuration that provides superior channel electrostatic control [6], [7]....
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TL;DR: In this paper, a 20-band sp3d5s* spin-orbit (SO) coupled atomistic tight-binding model coupled to a self-consistent Poisson solver is used for the valence-band dispersion calculation.
Abstract: Bandstructure effects in p-channel MOS (PMOS) transport of strongly quantized silicon nanowire FETs in various transport orientations are examined. A 20-band sp3d5s* spin-orbit (SO) coupled atomistic tight-binding model coupled to a self-consistent Poisson solver is used for the valence-band dispersion calculation. A ballistic FET model is used to evaluate the capacitance and current-voltage characteristics. The dispersion shapes and curvatures are strong functions of device size, lattice orientation, and bias, and cannot be described within the effective mass approximation. The anisotropy of the confinement mass in the different quantization directions can cause the charge to preferably accumulate in the (110) and then on the (112) rather than on (100) surfaces, leading to significant differences in the charge distributions for different wire orientations. The total gate capacitance of the nanowire FET devices is, however, very similar for all wires in all the investigated transport orientations ([100], [110], [111]), and is degraded from the oxide capacitance by ~30%. The [111] and then the [110] oriented nanowires indicate highest carrier velocities and better on-current performance compared to [100] wires. The dispersion features and quantization behavior, although a complicated function of physical and electrostatic confinement, can be explained at first order by looking at the anisotropic shape of the heavy-hole valence band.
62 citations
Cites background from "Ultra-Narrow Silicon Nanowire Gate-..."
...12 The (111) E(k) surface: The quantization of the [111] channels described earlier is determined from the (111) E(k) surface, with [1-10] and [11-2] quantized sides, shown in Fig....
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...Of course, the [100] wire can be quantized in the [110] and [1-10] directions....
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...6(d) along [111] perpendicular to the [1-10] direction....
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...Nanowire transistors of diameters even down to 3nm have already been demonstrated by various experimental groups [2, 3, 4, 5, 6]....
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...This is an effect resulting from the anisotropy of the heavy-hole quantization mass in the [1-10] and...
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References
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TL;DR: In this article, a review highlights the recent advances in the field, using work from this laboratory for illustration, and the understanding of general nanocrystal growth mechanisms serves as the foundation for the rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks.
Abstract: ▪ Abstract Semiconductor nanowires and nanotubes exhibit novel electronic and optical properties owing to their unique structural one-dimensionality and possible quantum confinement effects in two dimensions. With a broad selection of compositions and band structures, these one-dimensional semiconductor nanostructures are considered to be the critical components in a wide range of potential nanoscale device applications. To fully exploit these one-dimensional nanostructures, current research has focused on rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks, and integration of nanowire elements into complex functional architectures. Significant progress has been made in a few short years. This review highlights the recent advances in the field, using work from this laboratory for illustration. The understanding of general nanocrystal growth mechanisms serves as the foundation for the rational sy...
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TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
Abstract: This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.
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TL;DR: In this paper, a general approach for the synthesis of a broad range of semiconductor nanowires (NWs) with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism was introduced.
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