Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance
01 Dec 2006-pp 1-4
TL;DR: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.
Abstract: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well
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01 Jan 2012
TL;DR: In this paper, the authors presented a novel approach to fabricate thin film FinFETs having two independent side gates, self-aligned source/drain junctions and lithography-free channel length definition.
Abstract: We present a novel approach to fabricate thin film FinFETs having two independent side gates, self-aligned source/drain junctions and lithography-free channel length definition. N-type inversion-mode devices with sub-100nm channel length are fabricated on poly-silicon films with silicon nitride isolation layer. The dual poly-Si gates on the side walls of the vertical channel are defined using a damascene process. Devices showed good electrical performance (ION/IOFF ratio = 10 6 , SS = 120mV/dec, DIBL = 150mV/V) and wide range of threshold voltage tunability. The proposed method can be directly implemented on SOI or bulk wafers to provide high performance devices and has high potential for fabricating vertically stacked circuits.
Cites background from "Ultra-Narrow Silicon Nanowire Gate-..."
...Multi-gate devices have been researched for the last two decades to tackle scaling issues in planar CMOS transistors [1-2]....
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30 Dec 2010
TL;DR: In this paper, the variability induced by random discrete dopants in a gate-all-around silicon nanowire transistor was studied using the Non-Equilibrium Green Function formalism.
Abstract: In this paper we study the variability induced by random discrete dopants in a gate-all-around silicon nanowire transistor. The electron transport is described using the Non-Equilibrium Green Function formalism. Coupled-mode-space representations are used. A silicon nanowire transistor with 4.2×4.2 nm2 cross-section and two different channel lengths (6 nm and 12 nm) has been considered. The mobility associated with discrete dopants can be estimated from the averaged current voltage characteristics. The threshold voltage and subthreshold slope variability are greatly reduced in the longer channel length transistor. At the same time the on current variability associated with the resistance variability of the access regions is virtually independent of the channel length.
Cites background from "Ultra-Narrow Silicon Nanowire Gate-..."
...Nanowires with different cross sections and various channel lengths have been fabricated [1] [2] [3]....
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05 May 2008
TL;DR: The gate-all-around (GAA) fin-like poly-Si TFTs with multiple nanowire channels (MNCs) have been fabricated using a simple process to demonstrate high performance electrical characteristics as mentioned in this paper.
Abstract: The gate-all-around (GAA) fin-like poly-Si TFTs (FinTFTs) with multiple nanowire channels (MNCs) have been fabricated using a simple process to demonstrate high performance electrical characteristics. The fin-like nanowire (NW) channel with high body thickness-to-width ratio (TFin/WFin), approximately equals to one, was realized only with a sidewall-spacer formation. The unique suspending MNCs were also achieved to build the GAA structure. By the way, the GAA-MNC FinTFTs showed outstanding three-dimensional gate controllability and excellent electrical characteristics, which revealed a high ON/OFF current ratio (> 108), a low threshold voltage, a steep subthreshold swing, a near-free drain-induced barrier lowering and a good reliability. Therefore, such the high-performance GAA-MNC FinTFTs are very suitable for the applications in the system-on-panel (SOP) and three-dimensional (3D) circuits.
Cites background from "Ultra-Narrow Silicon Nanowire Gate-..."
...Recently, for single-crystalline Si-oninsulator (SOI) Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), lots of efforts on non-planar device structures have been developed for better gate controllability, such as double-gated, triple-gated, Π-gated, Ω-gated, NW finchannel, and GAA [7]-[18]....
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...Among those, GAA FETs together with the NW fin-channel have been reported to be the best structure to provide extreme geometry scaling and great electrical characteristics due to higher controllability and reducing grain-boundary defects[15]-[18]....
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...The aspect ratio TFin/WFin of each NW channel in the GAA-MNC TFT which equals to one is much larger than that in conventional planer TFT and thus features like a fin structure [9], [18], [22]....
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10 Oct 2008
TL;DR: In this paper, the authors studied the effect of acoustic phonon modulation on electron transport in a free-standing cylindrical semiconductor nanowire and derived the electron scattering rate and mobility.
Abstract: Impacts of modulated acoustic phonons on electron transport in a free-standing cylindrical semiconductor nanowire are theoretically studied. We formulate the electron scattering rate and mobility limited by the intra-valley acoustic phonon scattering mechanism, using bulk and modulated acoustic phonons in a [001]-directed Si nanowire. The scattering rate calculated using modulated acoustic phonons is larger than that with bulk phonons, and therefore the mobility is smaller when modulated acoustic phonons are incorporated. These results are attributed to an increase of the form factor due to acoustic phonon modulation. The form factor increase has a universality independent of wire material and radius.
Cites background from "Ultra-Narrow Silicon Nanowire Gate-..."
...…interaction, gate-all-around, electron mobility I. INTRODUCTION Recently, Si nanowire metal-oxide-semiconductor fieldeffect transistors (MOSFETs) have received considerable attention as one of the promising devices for future electronics due to their improved short channel immunity [1], [2]....
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TL;DR: In this paper, a functional gate metal-oxide-semiconductor field effect transistor that enables self-adjustment of threshold voltage (Vth) was developed for the ultralow power operation.
Abstract: A functional gate metal–oxide–semiconductor field-effect transistor that enables self-adjustment of threshold voltage (Vth) was developed for the ultralow power operation. The operating principle enables the on-current to be increased without increasing the off-current. Prototype devices were fabricated with complementary metal–oxide–semiconductor (CMOS) fabrication technology using a silicon-on-insulator substrate, and the fundamental device characteristics necessary for ultralow power operation were demonstrated with an emphasis on the device reliability. A negative Vth shift was caused by electron ejection from the poly-Si charge trap layer, and a positive Vth shift was caused by electron injection from the top gate electrode. A fabricated device endured 105 electron ejection-and-injection cycles when only a positive bias Vg was applied. Endurance characteristics of the fabricated devices showed that the number of cycles to oxide breakdown increased as the channel size decreased. The authors explained ...
References
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TL;DR: In this article, a review highlights the recent advances in the field, using work from this laboratory for illustration, and the understanding of general nanocrystal growth mechanisms serves as the foundation for the rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks.
Abstract: ▪ Abstract Semiconductor nanowires and nanotubes exhibit novel electronic and optical properties owing to their unique structural one-dimensionality and possible quantum confinement effects in two dimensions. With a broad selection of compositions and band structures, these one-dimensional semiconductor nanostructures are considered to be the critical components in a wide range of potential nanoscale device applications. To fully exploit these one-dimensional nanostructures, current research has focused on rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks, and integration of nanowire elements into complex functional architectures. Significant progress has been made in a few short years. This review highlights the recent advances in the field, using work from this laboratory for illustration. The understanding of general nanocrystal growth mechanisms serves as the foundation for the rational sy...
1,407 citations
TL;DR: In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.
Abstract: This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.
605 citations
TL;DR: In this paper, a scaling theory for fully-depleted, cylindrical MOSFET's was presented. But the scaling theory was derived from the cylinrical form of Poisson's equation by assuming a parabolic potential in the radial direction.
Abstract: We present a scaling theory for fully-depleted, cylindrical MOSFET's. This theory was derived from the cylindrical form of Poisson's equation by assuming a parabolic potential in the radial direction. Numerical device simulation data for subthreshold slope and DIBL were compared to the model to validate the formula. By employing the scaling theory a comparison with double-gate (DG) MOSFET's was carried out illustrating an improvement of up to 40% in the minimum effective channel length for the cylindrical device.
551 citations
TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
Abstract: This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.
477 citations
TL;DR: In this paper, a general approach for the synthesis of a broad range of semiconductor nanowires (NWs) with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism was introduced.
Abstract: Semiconductor nanowires (NWs) represent an ideal system for investigating low- dimensional physics and are expected to play an important role as both interconnects and functional device elements in nanoscale electronic and optoelectronic devices Here we re- view a series of key advances defining a new paradigm of bottom-up assembling integrated nanosystems using semiconductor NW building blocks We first introduce a general ap- proach for the synthesis of a broad range of semiconductor NWs with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism Subsequently, we describe rational strategies for the hierarchical assembly of NW building blocks into functional devices and complex architectures based on electric field or micro-fluidic flow Next, we discuss a vari- ety of new nanoscale electronic device concepts including crossed NW p-n diode and crossed NW field effect transistors (FETs) Reproducible assembly of these scalable crossed NW de- vice elements enables a catalog of integrated structures, including logic gates and computa- tional circuits Lastly, we describe a wide range of photonic and optoelectronic devices, in- cluding nanoscale light-emitting diodes (nanoLEDs), multicolor LED arrays, integrated nanoLED-nanoFET arrays, single nanowire waveguide, and single nanowire nanolaser The potential application of these nanoscale light sources for chemical and biological analyses is discussed
252 citations