Proceedings ArticleDOI
Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance
Navab Singh,Fong Yin Lim,W. W. Fang,S. C. Rustagi,L. K. Bera,Ajay Agarwal,C.H. Tung,Keat-Mun Hoe,S. R. Omampuliyur,D. Tripathi,A. O. Adeyeye,Guo-Qiang Lo,N. Balasubramanian,Dim-Lee Kwong +13 more
- pp 1-4
Reads0
Chats0
TLDR
Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.Abstract:
Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as wellread more
Citations
More filters
Journal ArticleDOI
Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part II–Experimental Results and Impacts on Device Variability
TL;DR: In this article, the correlation between line-edge roughness and line-width roughness was investigated by theoretical modeling and simulation, and the impacts of correlated LER/LWR in the channel of double-gate devices were investigated.
Journal ArticleDOI
Full 3D Quantum Transport Simulation of Atomistic Interface Roughness in Silicon Nanowire FETs
TL;DR: In this paper, the influence of interface roughness scattering (IRS) on the performances of silicon nanowire field effect transistors (NWFETs) is numerically investigated using a full 3D quantum transport simulator based on the atomistic sp3d5s* tight-binding model.
Journal ArticleDOI
Observation of Metal-Layer Stress on Si Nanowires in Gate-All-Around High- $\kappa$ /Metal-Gate Device Structures
Navab Singh,Wei-Wei Fang,S.C. Rustagi,K.D. Budharaju,Selin H. G. Teo,S. Mohanraj,G. Q. Lo,N. Balasubramanian,Dim-Lee Kwong +8 more
TL;DR: In this paper, the metal-gate layer on the Si nanowires formed by the top-down scheme was observed to viciously stretch and twist the straight wires, which suggests that the Si wires are subjected to large tensile strain.
Proceedings ArticleDOI
Gate-all-around Si-nanowire CMOS inverter logic fabricated using top-down approach
K.D. Buddharaju,Navab Singh,S.C. Rustagi,Selin H. G. Teo,L.Y. Wong,L.J. Tang,C.H. Tung,Guo-Qiang Lo,N. Balasubramanian,Dim-Lee Kwong +9 more
TL;DR: In this article, the authors present a monolithic integration of Gate-Ail-Around (GAA) Si-nanowire FETs into CMOS logic using top-down approach.
Journal ArticleDOI
Computational Study on the Performance of Si Nanowire pMOSFETs Based on the $k \cdot p$ Method
TL;DR: In this article, full-quantum device simulations on p-type Si nanowire field effect transistors based on the k · p method, using the k·p parameters tuned against the sp3s* tight-binding method, are carried out.
References
More filters
Journal ArticleDOI
Semiconductor nanowires and nanotubes
TL;DR: In this article, a review highlights the recent advances in the field, using work from this laboratory for illustration, and the understanding of general nanocrystal growth mechanisms serves as the foundation for the rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks.
Journal ArticleDOI
High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices
Navab Singh,Ajay Agarwal,Lakshmi Kanta Bera,Tsung-Yang Liow,R. Yang,S.C. Rustagi,C.H. Tung,Rakesh Kumar,G. Q. Lo,N. Balasubramanian,Dim-Lee Kwong +10 more
TL;DR: In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.
Journal ArticleDOI
Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's
C.P. Auth,James D. Plummer +1 more
TL;DR: In this paper, a scaling theory for fully-depleted, cylindrical MOSFET's was presented. But the scaling theory was derived from the cylinrical form of Poisson's equation by assuming a parabolic potential in the radial direction.
Journal ArticleDOI
Multiple-gate SOI MOSFETs: device design guidelines
TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
Journal ArticleDOI
Integrated nanoscale electronics and optoelectronics: Exploring nanoscale science and technology through semiconductor nanowires*
Yu Huang,Charles M. Lieber +1 more
TL;DR: In this paper, a general approach for the synthesis of a broad range of semiconductor nanowires (NWs) with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism was introduced.