Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance
01 Dec 2006-pp 1-4
TL;DR: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.
Abstract: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well
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TL;DR: Trigate SOI transistors have been modeled using the Poisson and Schrodinger equations, and current oscillations have been experimentally observed when the gate voltage is increased as discussed by the authors, which is due to a quantum-wire effect in which electron mobility is affected by intersubband scattering.
Abstract: Trigate SOI transistors have been modeled using the Poisson and Schrodinger equations. In devices with a large enough cross section, inversion channels form at the Si/SiO2 interfaces, but in devices with a small section, volume inversion is clearly visible. A transition between a one-dimensional density of states to a two-dimensional density of states is observed when the height of the fin is increased. Current oscillations are experimentally observed when the gate voltage is increased. These are due to a quantum-wire effect in which electron mobility is affected by intersubband scattering.
46 citations
TL;DR: In this article, the low-frequency noise in the subthreshold region of both n and p-type gate-all-around silicon nanowire transistors (SNWTs) is investigated.
Abstract: The low-frequency noise (LFN) in the subthreshold region of both n- and p-type gate-all-around silicon nanowire transistors (SNWTs) is investigated. The measured drain-current noise spectral density shows that the LFN in this regime can be well described by the mobility-fluctuation model due to the volume-inversion conduction behavior, and the Hooge parameter is extracted. The LFN in the SNWTs with channels oriented in lang010rang and lang110rang directions is compared. It shows that the observed mobility enhancement in the lang010rang direction for p-type transistors leads to a corresponding increase of the LFN level in the lang010rang direction compared with that in the lang110rang direction.
45 citations
Cites background from "Ultra-Narrow Silicon Nanowire Gate-..."
...In the subthreshold region of a lightly doped GAA SNWT, the drain-current level is proportional to the area of the cylindrical cross section for a given bias condition, and volume inversion takes place [4], [14]....
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...DUE to its better gate control, the gate-all-around (GAA) silicon nanowire transistor (SNWT) [1]–[4] is considered an important candidate for future CMOS scaling beyond the 32-nm node....
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...in [4], and the schematic view of the device is shown in Fig....
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TL;DR: In this article, the authors demonstrate that the lateral band-to-band tunneling component of gate-induced drain leakage (GIDL) leads to the formation of a parasitic bipolar junction transistor (BJT) in the OFF-state (gate voltage = 0.0 V) of nanowire FETs.
Abstract: In this paper, we demonstrate that the lateral band-to-band tunneling component of gate-induced drain leakage (GIDL) leads to the formation of a parasitic bipolar junction transistor (BJT) in the OFF-state (gate voltage = 0.0 V) of nanowire FETs (NW FETs). We discuss in detail the difference in the nature of GIDL, i.e., drain current dependence on the negative gate voltage ( ${V}_{\text {GS}} \le 0$ V) for different NW FET configurations. Furthermore, we show that the parasitic BJT action is significant in NW junctionless accumulation mode FET (JAMFET) and NW MOSFET in the OFF-state and diminishes as the gate voltage becomes negative. Using calibrated 3-D simulations, we investigate the impact of scaling on the NW FETs and show that the enhanced band gap due to the quantum confinement effect facilitates the scaling of the NW FETs to the sub-5-nm regime. In addition, we propose the use of a lightly doped drain extension to increase the ON-state to OFF-state current ratio ( ${I}_{ {{\scriptscriptstyle {ON}}}}/{I}_{ {\scriptscriptstyle {OFF}}})$ of NW JAMFET and NW MOSFET.
44 citations
TL;DR: The physics of carrier backscattering in 1-D and 2-D transistors is examined analytically and by numerical simulation in this paper, where the critical length for backscatter is somewhat longer than the kT length, and it depends on the shape of the channel potential profile.
Abstract: The physics of carrier backscattering in 1-D and 2-D transistors is examined analytically and by numerical simulation. An analytical formula for the backscattering coefficient is derived for elastic scattering in a 1-D channel. This formula shows that the critical length for backscattering is somewhat longer than the kT length, and it depends on the shape of the channel potential profile. For inelastic scattering, Monte Carlo (MC) simulations show that the critical length is related to the phonon energy. The MC simulations also show that although the scattering physics in 1-D and 2-D transistors is very different, the overall backscattering characteristics are surprisingly similar. For an elastic process, this similarity is due to the compensating effects of the scattering rate and the fraction of scattered carriers, which contribute to the backscattering coefficient. For an inelastic process, the critical length is determined from the phonon energy for both 1-D and 2-D channels.
44 citations
TL;DR: High-mobility junctionless gate-all-around nanowire field effect transistor with carrier mobility reaching 2000 cm(2)/V·s at room temperature with key scattering mechanisms limiting the carrier transport in these nanowires is reported.
Abstract: Ability to understand and model the performance limits of nanowire transistors is the key to design of next generation devices. Here, we report studies on high-mobility junction-less gate-all-around nanowire field effect transistor with carrier mobility reaching 2000 cm2/V.s at room temperature. Temperature-dependent transport measurements reveal activated transport at low temperatures due to surface donors, while at room temperature the transport shows a diffusive behavior. From the conductivity data, the extracted value of sound velocity in InAs nanowires is found to be an order less than the bulk. This low sound velocity is attributed to the extended crystal defects that ubiquitously appear in these nanowires. Analyzing the temperature-dependent mobility data, we identify the key scattering mechanisms limiting the carrier transport in these nanowires. Finally, using these scattering models, we perform drift-diffusion based transport simulations of a nanowire field-effect transistor and compare the device performances with experimental measurements. Our device modeling provides insight into performance limits of InAs nanowire transistors and can be used as a predictive methodology for nanowire-based integrated circuits.
43 citations
References
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TL;DR: In this article, a review highlights the recent advances in the field, using work from this laboratory for illustration, and the understanding of general nanocrystal growth mechanisms serves as the foundation for the rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks.
Abstract: ▪ Abstract Semiconductor nanowires and nanotubes exhibit novel electronic and optical properties owing to their unique structural one-dimensionality and possible quantum confinement effects in two dimensions. With a broad selection of compositions and band structures, these one-dimensional semiconductor nanostructures are considered to be the critical components in a wide range of potential nanoscale device applications. To fully exploit these one-dimensional nanostructures, current research has focused on rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks, and integration of nanowire elements into complex functional architectures. Significant progress has been made in a few short years. This review highlights the recent advances in the field, using work from this laboratory for illustration. The understanding of general nanocrystal growth mechanisms serves as the foundation for the rational sy...
1,407 citations
TL;DR: In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.
Abstract: This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.
605 citations
TL;DR: In this paper, a scaling theory for fully-depleted, cylindrical MOSFET's was presented. But the scaling theory was derived from the cylinrical form of Poisson's equation by assuming a parabolic potential in the radial direction.
Abstract: We present a scaling theory for fully-depleted, cylindrical MOSFET's. This theory was derived from the cylindrical form of Poisson's equation by assuming a parabolic potential in the radial direction. Numerical device simulation data for subthreshold slope and DIBL were compared to the model to validate the formula. By employing the scaling theory a comparison with double-gate (DG) MOSFET's was carried out illustrating an improvement of up to 40% in the minimum effective channel length for the cylindrical device.
551 citations
TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
Abstract: This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.
477 citations
TL;DR: In this paper, a general approach for the synthesis of a broad range of semiconductor nanowires (NWs) with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism was introduced.
Abstract: Semiconductor nanowires (NWs) represent an ideal system for investigating low- dimensional physics and are expected to play an important role as both interconnects and functional device elements in nanoscale electronic and optoelectronic devices Here we re- view a series of key advances defining a new paradigm of bottom-up assembling integrated nanosystems using semiconductor NW building blocks We first introduce a general ap- proach for the synthesis of a broad range of semiconductor NWs with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism Subsequently, we describe rational strategies for the hierarchical assembly of NW building blocks into functional devices and complex architectures based on electric field or micro-fluidic flow Next, we discuss a vari- ety of new nanoscale electronic device concepts including crossed NW p-n diode and crossed NW field effect transistors (FETs) Reproducible assembly of these scalable crossed NW de- vice elements enables a catalog of integrated structures, including logic gates and computa- tional circuits Lastly, we describe a wide range of photonic and optoelectronic devices, in- cluding nanoscale light-emitting diodes (nanoLEDs), multicolor LED arrays, integrated nanoLED-nanoFET arrays, single nanowire waveguide, and single nanowire nanolaser The potential application of these nanoscale light sources for chemical and biological analyses is discussed
252 citations