Proceedings ArticleDOI
Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance
Navab Singh,Fong Yin Lim,W. W. Fang,S. C. Rustagi,L. K. Bera,Ajay Agarwal,C.H. Tung,Keat-Mun Hoe,S. R. Omampuliyur,D. Tripathi,A. O. Adeyeye,Guo-Qiang Lo,N. Balasubramanian,Dim-Lee Kwong +13 more
- pp 1-4
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TLDR
Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.Abstract:
Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as wellread more
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Journal ArticleDOI
Demonstration of Schottky Barrier NMOS Transistors With Erbium Silicided Source/Drain and Silicon Nanowire Channel
Eu Jin Tan,Kin Leong Pey,Navab Singh,Guo-Qiang Lo,Dongzhi Chi,Yoke King Chin,Keat Mun Hoe,Guangda Cui,Pooi See Lee +8 more
TL;DR: In this paper, the authors have fabricated silicon nanowire N-MOSFETs using erbium disilicide (ErSi2-x) in a Schottky source/drain back-gated architecture.
Journal ArticleDOI
Radiation Effects in Si-NW GAA FET and CMOS Inverter: A TCAD Simulation Study
Gaurav Kaushal,Surendra S. Rathod,S. Maheshwaram,Sanjeev Kumar Manhas,A. K. Saxena,Sudeb Dasgupta +5 more
TL;DR: In this article, the response of silicon-nanowire (Si-NW) gate-all-around (GAA) field effect transistor to total ionizing dose (TID) effects and assessed the impact of single-event effects (SEEs) in simple inverter circuit built from such devices.
Journal ArticleDOI
Unified Compact Model for Nanowire Transistors Including Quantum Effects and Quasi-Ballistic Transport
TL;DR: In this paper, a surface potential-based compact model for nanowire FETs is presented, which considers 1-D electrostatics along with the effect of multiple energy subbands.
Journal ArticleDOI
Theoretical Study of Ballistic Transport in Silicon Nanowire and Graphene Nanoribbon Field-Effect Transistors Using Empirical Pseudopotentials
TL;DR: In this article, the performance of gate-all-around field effect transistors (FETs) with channels consisting of armchair-edge graphene nanoribbons (aGNRs) of various widths and silicon nanowires with square cross sections was analyzed.
Journal ArticleDOI
Threshold Voltage Control by Substrate Bias in 10-nm-Diameter Tri-Gate Nanowire MOSFET on Ultrathin BOX
TL;DR: In this paper, the substrate bias effect in 10-nm-diameter tri-gate nanowire (NW) MOSFETs on ultrathin BOX was investigated.
References
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TL;DR: In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.
Journal ArticleDOI
Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's
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TL;DR: In this paper, a scaling theory for fully-depleted, cylindrical MOSFET's was presented. But the scaling theory was derived from the cylinrical form of Poisson's equation by assuming a parabolic potential in the radial direction.
Journal ArticleDOI
Multiple-gate SOI MOSFETs: device design guidelines
TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
Journal ArticleDOI
Integrated nanoscale electronics and optoelectronics: Exploring nanoscale science and technology through semiconductor nanowires*
Yu Huang,Charles M. Lieber +1 more
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