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Book ChapterDOI

Ultra Power Efficient Melior Quantum Multiplier with Reduced Ancilla and Garbage Outputs

TL;DR: In this paper, the authors proposed an optimized Partial Product Generation and Multi-Operand Addition using primitive Quantum gates to reduce the count of Ancilla and Garbage Outputs.
Abstract: Reversible Logic is an emerging field of research which finds its applications in low power computing, Nanotechnology and Quantum Computing. Reversible circuits should have one to one mapping i.e. one input can have only one output so that input vectors can be realized using output vectors. Reversible Circuits require Ancilla(constant inputs) and Garbage Outputs to retain reversibility. An efficient Reversible Circuit can be designed by optimizing their performance parameters. In this paper a \(4 \times 4\) Melior Quantum Multiplier has been proposed which consists of an optimized Partial Product Generation and Multi-Operand Addition using primitive Quantum gates to reduce the count of Ancilla and Garbage Outputs. This proposed multiplier shows an improvement of 21.73% and 18.18% reduction of Ancilla and Garbage Outputs respectively. This multiplier has been implemented in Cadence Virtuoso with average power dissipation of 106.79 nW at 45 nm technology node and used in the implementation of a Linear Phase FIR filter with an average power dissipation of 456.1 nW.
Citations
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Book ChapterDOI
14 Nov 2022
TL;DR: In this article , a novel arithmetic multiplier that can be used for cryptographic applications is designed using residue number system (RNS), and all the simulations have been implemented using Cadence Design Framework with 45 nm, and results are encouraging.
Abstract: As in the digital era, there will always be a demand for high-speed algorithms and techniques that can accelerate computations. Arithmetic computation can be performed more quickly with the help of VLSI fabrication techniques and the residue number system (RNS). In this paper, a novel arithmetic multiplier that can be used for cryptographic applications is designed using RNS. In general, the binary numbers are converted into residues, and then, the multiplication operation takes place with residues. At the end, these residues are converted back to binary numbers using the Chinese remainder theorem (CRT). All the simulations have been implemented using Cadence Design Framework with 45 nm, and results are encouraging. It is observed that the delay savings are improved by 78%.
References
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01 Jan 2008
TL;DR: In this paper, the authors proposed a 4x4 bit reversible multiplier circuit, which is faster and has lower hardware complexity compared to the existing designs in terms of number of gates and number of garbage outputs.
Abstract: Reversible computation is of the growing interests to power minimization having applications in low power CMOS design, quantum computing, optical information processing, DNA computing, bioinformatics and nanotechnology. This paper proposes a novel 4x4 bit reversible Multiplier circuit. It is faster and has lower hardware complexity compared to the existing designs. In addition, the proposed reversible multiplier is better than the existing counterparts in term of number of gates and number of garbage outputs. Haghparast and Navi recently proposed a 4x4 reversible gate called "MKG". The reversible MKG gate can work singly as a reversible full adder. In this paper we use MKG gates to construct the reversible multiplier circuit. The proposed reversible multiplier circuit can multiply two 4-bits binary numbers. It can be generalized for NxN bit multiplication.

79 citations

Proceedings ArticleDOI
05 Jan 2014
TL;DR: The proposed binary tree based design methodology for NxN reversible quantum multiplier performs the addition of partial products in parallel using the reversible ripple quantum adders with no garbage output and ancilla bit, thereby minimizing the number of anCilla and garbage bits used in the design.
Abstract: Reversible logic has emerged as a promising computing paradigm having applications in quantum computing, optical computing, dissipation less computing and low power computing etc. In reversible logic there exists a one to one mapping between the input and output vectors. Reversible circuits require constant ancilla inputs for reconfiguration of gate functions and garbage outputs that help in keeping reversibility. Quantum circuits of many qubits are extremely difficult to realize thus reduction in the number of ancilla inputs and the garbage outputs is the primary goal of optimization. In existing literature researchers have proposed several designs of reversible quantum multipliers based on reversible full adders and reversible half adders. The use of reversible full adders and the half adders for the addition of partial products increases the overhead in terms of number of ancilla inputs and number of garbage outputs. This paper presents a binary tree based design methodology for a NxN reversible quantum multiplier. The proposed binary tree based design methodology for NxN reversible quantum multiplier performs the addition of partial products in parallel using the reversible ripple quantum adders with no garbage output and ancilla bit, thereby minimizing the number of ancilla and garbage bits used in the design. The proposed design methodology shows the improvement of 17.86% to 60.34% in terms of ancilla inputs; and 21.43% to 52.17% in terms of garbage outputs compared to all the existing reversible quantum multiplier designs.

58 citations

Proceedings ArticleDOI
25 Jun 2010
TL;DR: It has been shown that the proposed reversible logic device in designing multiplier circuits can work singly as a reversible full adder and it has been demonstrated thatThe proposed design of reversible multiplier circuit needs fewer garbage outputs and constant inputs.
Abstract: Multiplier circuits play an important role in reversible computation, which is helpful in diverse areas such as low power CMOS design, optical computing, DNA computing and bioinformatics, quantum computing and nanotechnology. In this paper a new reversible device called MFA (modified full adder) is used to design a novel reversible 4-bit binary multiplier circuit with low hardware complexity. It has been shown that the proposed reversible logic device in designing multiplier circuits can work singly as a reversible full adder. Furthermore, it has been demonstrated that the proposed design of reversible multiplier circuit needs fewer garbage outputs and constant inputs. The proposed multiplier can be generalized for N×N bit multiplication. Thus, this job will be of significant value as the technologies mature.

24 citations

Proceedings ArticleDOI
01 Jan 2018
TL;DR: Reversible logic technology is used for decreasing the energy dispersion, heatwave dissipation, increasing rapidness etc, and it is used to maximize the speed and reducing energy consumption.
Abstract: Heat is an important issue in VLSI circuits. But the reversible logic gives zero amount of heat dissipation. So, its an important role in nanotechnology, less energy complementary metal oxide semiconductor [CMOS] designs etc. It has been realized that quantum computing is one of the latest technologies using reversible logic gates. It is contemplating that accumulation extension of transistor density, energy desolation will command their limits in ordinary technologies. In ordinary area or range during the logic influence bits of orientation is erased resulting gratification of power in powerful amount. In the terms of reversible logic results are not lost.[1] This minimize the delays but at the amount of little hardware. So we can use reversible logic technology for decreasing the energy dispersion, heatwave dissipation, increasing rapidness etc. So it is used to maximize the speed and reducing energy consumption. In this, we can describe following reversible logic gates like fredkin, peres, Feynmen and toffoli gate etc.

12 citations

01 Jan 2013
TL;DR: The proposed array multiplier design uses 96 less transistor count and saves 2.82% of total power, 13.24% of more speed and 15.69% less power delay product when being compared with the conventional array multiplier in 32nm MOSFET Technology using HSPICE.
Abstract: ---------------------------------------------------------------------------------------------------------------Multiplier is one of the basic functional unit in digital signal processor. Most high performance DSP systems rely on hardware multiplication to achieve high data throughput. In this paper a low power and low area array multiplier is proposed. The conventional array multiplier is synthesised using 16T full adder cell. In conventional array multiplier the final stage of addition is removed and the carry bits are given to the input of the next left column input, thereby causing a large trade off in power and area. The proposed array multiplier is synthesised using 10T full adder cell. The proposed array multiplier design uses 96 less transistor count and saves 2.82% of total power, 13.24% of more speed and 15.69% less power delay product when being compared with the conventional array multiplier in 32nm MOSFET Technology using HSPICE.

11 citations