Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
More filters
27 May 2007
TL;DR: A novel calibration technique to compensate for DAC element mismatches in bandpass multibit delta-sigma (DeltaSigma) modulators is presented, compatible with binary weighted element DACs and the storage requirements for the calibrated coefficients increases only linearly with the number of quantizer bits.
Abstract: We present a novel calibration technique to compensate for DAC element mismatches in bandpass multibit delta-sigma (DeltaSigma) modulators. The proposed technique is purely digital and requires only a minor modification to the modulator loop. It is compatible with binary weighted element DACs and the storage requirements for the calibrated coefficients increases only linearly with the number of quantizer bits. The calibration is performed without breaking the loop, which allows continuous tracking of environmental drifts. Simulation results show a peak signal to noise and distortion ratio (SNDR) of 68 dB after calibration for a DAC with plusmn1% mismatches, a sinusoid input signal near 1/4 of the sampling frequency and an oversampling ratio of only 10. Those results represent a 26 dB improvement over the non-calibrated case while being within 2 dB of an ideal-DAC case.
10 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...I. INTRODUCTION Bandpass multibit ∆Σ modulators are attractive for communication systems because they allow digitization early in the receiver’s chain while achieving high resolution at low oversampling ratios (OSR) [1]....
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...Bandpass multibit ∆Σ modulators are attractive for communication systems because they allow digitization early in the receiver’s chain while achieving high resolution at low oversampling ratios (OSR) [1]....
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...When the feedback DAC N2 is nonlinear, not only does harmonic distortion increase, but the noise floor also increases due to the folding of high-frequency quantization noise to lower frequencies [1]....
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...The loop filter coefficients have been found using the Matlab “delsig” toolbox [8], for a 4th order bandpass modulator with optimized NTF zeros, OSR = 10 and two STF zeros at DC....
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...The selected loop filter structure is the CRFB [1] because it allows placement of the NTF zeros optimally, which improves SNR, especially for a low OSR....
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TL;DR: A novel frequency-agile and reconfigurable transfer function design, allowing digital post-compensation of the MFI, is proposed, based on a novel closed-form transfer function model for higher-order quadrature Σ� Δ modulators (QΣΔMs) under implementation inaccuracies, proposed herein.
Abstract: A quadrature ΣΔ analog-to-digital converter (ADC) is a promising solution for intermediate frequency digitizing software defined cognitive radio (CR) receivers because of, e.g., multiband capability and power efficiency. However, inherent coefficient mismatches between the in-phase and quadrature rails can severely damage the performance of such receiver by creating mirror-frequency interference (MFI). In this article, a novel frequency-agile and reconfigurable transfer function design, allowing digital post-compensation of the MFI, is proposed. The design is based on a novel closed-form transfer function model for higher-order quadrature ΣΔ modulators (QΣΔMs) under implementation inaccuracies, proposed herein. By doing the compensation in digital domain, it is possible to take into account all error-sources of the receiver chain at once, including, e.g., a quadrature mixer before the ADC. This capability is obtained by preserving the mirror-band signal information and using the noise transfer function of a QΣΔM to remove quantization noise from therein. This is demonstrated in a multiband scenario aimed for CR receivers, where a number of frequency channels can be received and detected in parallel. Practical examples of the transfer function analysis under implementation inaccuracies and the post-compensation performance are given with a two-stage QΣΔM, having stage-orders of four, allowing eighth-order noise shaping.
10 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...The ΣΔ modulator architecture considered in this article is a complex-valued version of cascaded integrators with distributed feedback and input [6], [28]....
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...The stability is improved by limiting the out-ofband gain of the NTF, which is one of the most important factors in this aspect [28]....
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...For the stability of the modulator, [28] gives two criteria; for single-bit modulators is required that maxω ∣∣NTF (ejω)∣∣ < 1....
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20 May 2012
TL;DR: The synthesis of low depth command streams for power bridges is considered, with regards to drives for ac motors, and it is shown that ΔΣM may offer some commonly unexploited forms of tuning and may lead to a more flexible choice of placement on the performance space.
Abstract: The synthesis of low depth command streams for power bridges is considered, with regards to drives for ac motors. Focus is on the exploitation of the degrees of freedom still available once the command rate is set. Using a nonlinear motor model, different options are evaluated up to the mechanical output. Options such as Delta Sigma Modulation (ΔΣM) and Pulse Width Modulation (PWM) are associated to tuples of merit factors defining points in a performance space. Standard ΔΣM is shown to favor perceived drive quality, while PWM helps keeping the switching rate low. Interpreting both PWM and ΔΣM as heuristics for Pulse Density Modulation (PDM), it is shown that ΔΣM may offer some commonly unexploited forms of tuning and may lead to a more flexible choice of placement on the performance space.
10 citations
TL;DR: In this paper, a broadband high-efficiency supply modulator is proposed, with a node controlled by the ΔΣ modulator's output, consisting of a conventional Class-E amplifier and a Class E rectifier, and its performance for broadband envelopes amplification is analyzed using numerical difference equations.
Abstract: In this paper, a broadband high-efficiency supply modulator is proposed. This modulator, with a node controlled by ΔΣ modulator's output, consists of a conventional Class-E amplifier and a Class-E rectifier. The configurations and operation principles of this modulator are introduced to explain the envelope reconstruction process. The performance of this modulator in steady state is analyzed to show the reason for high-efficiency operations assisted by a shunt diode, especially for short-circuited load resistance. Its performance for broadband envelopes amplification is analyzed using numerical difference equations. The results show that efficiency degradation and nonlinearity of this modulator are inevitable due to transient responses. The most significant factors related to the performance degradation, such as switch loss and conduction loss, are determined and verified by numerical simulations. The simulations for one-carrier wavelength code-division multiple-access (WCDMA) envelopes show that over 80% average efficiency and normalized mean square error (NMSE) of -16 dB can be obtained in numerical examples even considering the nonidealities. An experimental supply modulator is given to verify the proposed modulator. In this experiment, 48.6% average efficiency and NMSE of -15.9 dB are measured for WCDMA envelopes of 6.1-dB peak-to-average-power ratio.
10 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...Although the ZVS condition cannot be always kept in transient state, especially when T2 is controlled by random pulses, the analysis for steady state is still important to the design....
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...The following examples only provide an example without the whole scenario....
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18 May 2008
TL;DR: This chip integrated a 1.5 bit delta sigma modulator and full bridge power stages with programmable dead time control circuits, 0.02% THD+N ratio, 16 dB dynamic range and 8% power efficiency improvement are achieved in a 0.35 um polycide CMOS technology.
Abstract: This paper describes the design and implementation of a 1.5 bit 5th order CT/DT delta sigma class D amplifier. This chip integrated a 1.5 bit delta sigma modulator and full bridge power stages with programmable dead time control circuits. With the proposed 1.5 bit delta sigma modulator and dead time calibration techniques, 0.02% THD+N ratio, 16 dB dynamic range and 8% power efficiency improvement are achieved in a 0.35 um polycide CMOS technology. This chip consumes 7.8 mA and works at 3 V to 5.5 V supply range. The die area is 6 mm2.
10 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...There are many topologies to get one set of coefficients for the loop filter with a given specification [2][3]....
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References
More filters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations