scispace - formally typeset
Search or ask a question
Book

Understanding Delta-Sigma Data Converters

TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

Content maybe subject to copyright    Report

Citations
More filters
Journal ArticleDOI
TL;DR: A new iterative algorithm is used to convert analog signals to digital (A/D) using an asynchronous A/D converter, which is a realtime system, which encodes the amplitude information of the analog signal into a time sequence.
Abstract: In this paper, a new iterative algorithm is used to convert analog signals to digital (A/D) using an asynchronous A/D converter. It is a realtime system, which encodes the amplitude information of the analog signal into a time sequence. In particular, using asynchronous systems for data conversion is an effective technique in order to reduce power consumption. The decoder should recover original signal from irregular samples. If a more intelligent reconstruction technique is used for decoding, signals with higher bandwidth can be digitized. In this work, we employ delta- and sigma-delta level-crossing sampling schemes. These asynchronous A/D converters are simple to implement and have very good performance with lower power consumption.

9 citations


Cites background from "Understanding Delta-Sigma Data Conv..."

  • ...The principle of the sigma-delta architecture is to make rough evaluations of the signal, to measure the error, and then integrate and compensate for that error [11]....

    [...]

Proceedings ArticleDOI
03 Apr 2012
TL;DR: The Coding Efficiency in multi-bit delta-sigma based transmitters has been improved significantly by only adjusting the quantizer's threshold values, and the transmitter's linearity should be compromised to achieve this.
Abstract: In this paper the Coding Efficiency in multi-bit delta-sigma based transmitters has been improved significantly by only adjusting the quantizer's threshold values. To achieve this, the transmitter's linearity should be compromised. Usually the space between thresholds in a quantizer of a multi-bit delta-sigma modulator is uniform which not the optimum choice is for Coding Efficiency. For an LTE signal with 3.84 MHz bandwidth and 16 times oversampling, the Coding Efficiency improves from 11.3% to 23.9% and from 31.2% to 48.7% by only changing the quantizer's threshold values in a 3-level and a 5-level multi-bit delta-sigma modulators respectively. However, their Signal to Noise and Distortion Ratios degrade from 45.1 dB to 35.0 dB and from 51 dB to 42 dB respectively.

9 citations


Cites background from "Understanding Delta-Sigma Data Conv..."

  • ...In two-bit (two-level) DSMs case, a switching-mode PA (SMPA) with theoretically 100% efficiency can be used [4]....

    [...]

  • ...Finally, section IV explains the effect of the quantizer’s threshold values on the Ceff and signal qualities and how to select the optimum threshold values for a DSM’s quantizer....

    [...]

  • ...In spite of noise shaping in DSMs [5], some part of this noise locates in inband of the desired signal and degrades the signal quality....

    [...]

  • ...The idea is tested and validated by using different signal standards and different DSMs....

    [...]

  • ...There have been some studies, aiming to minimize the quantization noise at the output of MBDSMs by adjusting threshold values of their quantizars [7][8]....

    [...]

Journal ArticleDOI
TL;DR: The effect of MOS capacitance nonlinearity on the overall performance of discrete-time sigma-delta modulators is investigated, and a behavioral-level model of a MOSFET-only switched-capacitor (SC) integrator is proposed, and enables characterizing the transfer behavior of MFA-only modulators.
Abstract: Digital integrated circuits (ICs) can be integrated in low-cost digital CMOS technologies with less number of masks than a mixed-signal CMOS technology. This property, however, limits the access to reliable analog components such as linear capacitors and linear inductors. Regardless of the CMOS process, sigma-delta (ΣΔ) modulation of analog signals can be fulfilled by using ordinary MOS devices as capacitors. Called as MOS capacitors (MOSCAPs), these elements illustrate nonlinear C-V characteristic, although the thin gate oxide layer results a high capacitance per unit area. In this article, we investigate the effect of MOS capacitance nonlinearity on the overall performance of discrete-time sigma-delta modulators. To this end, a behavioral-level model of a MOSFET-only switched-capacitor (SC) integrator is proposed, and enables characterizing the transfer behavior of MOSFET-only modulators. The proposed model is used to analyze the linearity and to select a suitable architecture for the modulator. It helps to decide proper structure of each MOSCAP depending on its significance on the output linearity. In virtue of the new model, behavioral-level simulation of a 1-V 12-bit 20MS/s MOSFET-only 2 + 2 sturdy MASH (SMASH) modulator matches well to circuit-level simulations in 90-nm digital CMOS technology. For a −1.4 dB, 19.7 kHz input and an oversampling ratio of 16, the modulator achieves over 72 dB signal-to-noise plus distortion ratio (SNDR), only 3 dB lower than a conventional design based on linear metal-insulator-metal (MIM) capacitors.

9 citations

Journal ArticleDOI
TL;DR: In this article, a direct digital converter for Wheatstone bridge sensors is presented, which is realized with commercial off-the-shelf components, and the power efficiency of the readout is enhanced by embedding the bridge sensor in a second-order continuous-time sigma-delta modulator.
Abstract: This paper presents a direct digital converter for Wheatstone bridge sensors, which is realized with commercial off-the-shelf components. The power efficiency of the readout is enhanced by embedding the bridge sensor in a second-order continuous-time sigma-delta modulator ( ${\mathrm{ CT}}\Delta \Sigma {\mathrm{ M}}$ ). By directly digitizing the output signal of a Wheatstone bridge in the current mode, the noise performance is dominated by the operational amplifier in the first integrator and the bridge sensor. To demonstrate the performance of the proposed circuit, an MEMS piezoresistive differential pressure sensor is used. Measurement results show that a resolution of 12.7 mPa $_{\mathrm {{rms}}}$ (0.41 $\text{m}\Omega _{\mathrm {{rms}}}$ ), with a 0.5-ms conversion time, can be achieved. Powered by 5 V, the circuit and the bridge sensor draw 9.55 and 7.58 mW, respectively.

9 citations


Cites background from "Understanding Delta-Sigma Data Conv..."

  • ...The absence of an anti-aliasing filter makes CT Modulators more energy-efficient compared to their DT counterparts [18]....

    [...]

  • ...Moreover, due to the inherent anti-aliasing property of CT Modulators, sampling does not increase the in-band noise [18]....

    [...]

  • ...8, is used here due to its inherent linearity [18]....

    [...]

Proceedings ArticleDOI
16 May 2008
TL;DR: In this paper, the inner current loop is kept analog with analog comparator and SR latch, and the outer voltage loop is digital with Sigma-Delta modulator and low resolution DAC.
Abstract: Sigma-delta (SigmaDelta) modulators offer cost advantages in digitally controlled power supplies. Due to its noise shaping, high resolution, high speed ADCs and DACs are not necessary for digital control. This paper presents a low cost current-mode controller. The outer voltage loop is digital with SigmaDelta modulator and low resolution DAC. The inner current loop is kept analog with analog comparator and SR latch. An experimental circuit includes a SigmaDelta modulator test chip, a controller implemented on an FPGA, and a 30 V-to 3.3 V 10 W fly-back converter operating at 100 kHz. Experimental results demonstrate this mixed structure is a suitable solution for digital power supplies.

9 citations


Cites background from "Understanding Delta-Sigma Data Conv..."

  • ...They are able to achieve over 20 effective-number-of-bits (ENOB) resolutions [10]....

    [...]

References
More filters
Journal ArticleDOI
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >

399 citations

Journal ArticleDOI
James C. Candy1
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.

342 citations

Journal ArticleDOI
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.

284 citations

Book ChapterDOI
James C. Candy1, O. Benjamin1
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.

255 citations

Journal ArticleDOI
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >

211 citations