Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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TL;DR: Burst-mode operation of power amplifiers (PAs) is a promising concept towards higher power efficiency in radio frequency (RF) transmitters, but conventional digital pulse-width modulated signals contain a large amount of distortion that cannot be removed by the reconstruction filter in a satisfactory manner.
Abstract: Burst-mode operation of power amplifiers (PAs) is a promising concept towards higher power efficiency in radio frequency (RF) transmitters. Such transmitters use pulse-width modulation (PWM) to create the driving signal for the PA, and a reconstruction filter after amplification to obtain the transmission signal. However, conventional digital pulse-width modulated signals contain a large amount of distortion that cannot be removed by the reconstruction filter in a satisfactory manner.
76 citations
Cites methods from "Understanding Delta-Sigma Data Conv..."
...Common methods for encoding amplitude information into a square-wave signal are -modulation [11] and pulse-width...
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TL;DR: In this paper, a noise-shaped synchronous buck dc-dc converter based on a third-order active-passive continuous-time sigma-delta modulator is presented.
Abstract: A noise-shaped synchronous buck dc-dc converter based on a third-order active-passive continuous-time sigma-delta modulator is presented Detailed system modeling and loop design methodology are discussed A dual-mode compensator is proposed to achieve the loop stability over a wide load range The light-load efficiency is improved by the proposed dynamic width control and sigma-delta pulse-skip mode techniques In order to get a fast transient response, the linear-nonlinear control is adopted Moreover, an on-chip soft-start circuit is proposed to save the system cost The proposed converter has been fabricated using Chartered 035- μm 2P4M dual-gate mixed-signal CMOS process Experimental results show that the converter effectively suppresses the switching harmonics at both continuous conduction mode and discontinuous conduction mode Compared with the conventional pulsewidth modulation operation, the first harmonic peak has been reduced by -35 dB The converter achieves a peak efficiency of 92% at 200 mA, and a light-load efficiency of 78% at 5 mA With the load current skipping between 50 and 450 mA, the maximum output overshoot voltage is 87 mV, and the recovery time is below 12 μs The start-up time for the output voltage is 160 μs By configuring the soft-start circuit, this time can be prolonged to 680 μs The area of the whole chip is 14 mm2
75 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...put of a single-bit SDM exhibits a random instantaneous frequency [15]....
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...of noise shaping is proportional to the order of SDM, but a higher order SDM is less stable [15]....
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...For a purer output spectrum, dither or a higher order SDM have to be adopted [12], [13], [15]....
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...An active-RC integrator is used in the first stage to guarantee a high linearity [15]....
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TL;DR: This paper describes a wideband high-linearity ADC that uses noise coupling combined with time interleaving to increase the effective order of the noise-shaping loops, provides dithering, and prevents tone generation in all loops.
Abstract: This paper describes a wideband high-linearity ?? ADC. It uses noise coupling combined with time interleaving. Two versions of a two-channel time-interleaved noise-coupled ?? ADC were realized in a 0.18-?m CMOS technology. Noise coupling between the channels increases the effective order of the noise-shaping loops, provides dithering, and prevents tone generation in all loops. Time interleaving enhances the effects of noise coupling. Using a 1.5 V supply, the device achieved excellent linearity (SFDR>100 dB, THD=-98 dB) and an SNDR of 79 dB in a 4.2 MHz signal band.
75 citations
TL;DR: A discrete-time audio ΔΣ modulator for a MEMS microphone with digital output is presented that features a scalable signal bandwidth to also support ultrasonic frequencies for proximity sensing applications such as gesture recognition.
Abstract: A discrete-time audio ΔΣ modulator for a MEMS microphone with digital output is presented that features a scalable signal bandwidth to also support ultrasonic frequencies for proximity sensing applications such as gesture recognition. The modulator achieves low power consumption and a small die area by using simple digital inverter instead of OTAs. To increase the robustness of the inverter approach, an LDO is used to provide an internally generated supply which regulates the inverter bias point. The LDO also improves the power supply rejection of the pseudo-differential architecture to above 78 dB. The presented ΔΣ modulator supports a scalable signal bandwidth up to 100 kHz, by dynamically adjusting the internal supply voltage depending on the sampling frequency. In the nominal 20-kHz audio band, it dissipates 140 μW from a minimum 1.5-V supply and achieves a DR of 92.6 dB , a SNDR of 87.9 dB, and a THD of -102.7 dB, respectively.
74 citations
Cites methods from "Understanding Delta-Sigma Data Conv..."
...To have a fair comparison, the proposed by Schreier will be used for the comparison [39]:...
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01 Jan 2006
TL;DR: It is shown that NTFs with optimized zeros result in lower jitter noise than those with all zeros at the origin, and a design procedure is proposed that minimizes the sum of the quantization and jitters.
Abstract: where(GTisthevariance oftheclock jitter. Clearly, Ge2j is We examine noiseduetolokjtteisid ependent
73 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...The bandwidth requirements for the active elements in the loop are relaxed [1], which results in a lower power consumption....
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...In such a scenario, STF peaking can be mitigated by appropriate choice of the loop filter topology [1]....
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...These assumptions tend to be largely valid when a multibit quantizer is used in the loop [1]....
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...For a given and NTF order, the OBG for a modulator with optimally spread passband zeros is smaller than that of an NTF with all zeros at the origin [1], as shown with a fourth-order Fig....
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References
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TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations