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Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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TL;DR: The improved CDSM can be implemented using existing optimization tools, which reduces considerably the number of iterations and the computational effort, and can target different coexistence scenarios without the need of redesign, unlike other known methods.
Abstract: This paper presents a complex delta–sigma modulator (CDSM) designed for integration in a digital transmitter chain targeting multi-standard coexistence with nearby receivers. The use of a DSM has the advantage of increased performance in terms of signal-to-noise-ratio in the band of interest. However, the resulting out-of-band noise becomes an issue for multi-standard coexistence, thus increasing the complexity of the subsequent filtering stage. This constraint could be relaxed in the DSM stage, by placing a complex zero near the frequency band, where a low noise level is needed. This is achieved by cross coupling the in-phase (I) and quadrature (Q) channels, thus obtaining a CDSM. A review of known design methods for CDSM revealed limitations regarding the poles/zeros optimization, and the configurability of the complex zeros placement. The proposed architecture introduces two additional cross couplings from the I and Q quantizers outputs in order to decorrelate the zeros placement and the poles optimization problem. Hence, the improved CDSM can be implemented using existing optimization tools, which reduces considerably the number of iterations and the computational effort. In addition, the resulting modulator can target different coexistence scenarios without the need of redesign, unlike other known methods. Simulation results show a noise level reduction of approximately 20–30-dB near specific frequency bands by the proposed CDSM scheme with respect to standard DSM. Finally, we show an efficient coarse/fine configurability mechanism, which is obtained when introducing additional delays in the cross-coupling paths.
8 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...A detailed description of this tool and the associated functions can be found in [12]....
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TL;DR: Noise and distortion characteristics of the EPWM transmitter in the amplification of the OFDM signal are presented and results showed good agreement with the analytical results despite the use of the linear-approximation gain plus noise model.
Abstract: The envelope pulse-width modulation (EPWM) transmitter has been proposed to address the power efficiency issue in the linear amplification of multicarrier signals. However, the delta-sigma (Δ-∑) modulator in the EPWM transmitter generates quantization noise that degrades the output signal quality. In this paper, noise and distortion characteristics of the EPWM transmitter in the amplification of the OFDM signal are presented. First, quantization noise and distortion due to amplitude clipping are analyzed. Theoretical noise power spectral density (PSD) and error vector magnitude (EVM) are obtained as functions of the Δ-∑ modulator and input signal parameters. Then, simulations to validate the noise and distortion characteristics are done using the IEEE 802.11a OFDM signal and first- and second-order Δ-∑ modulators. The effects of bandpass filtering on EVM and adjacent channel leakage power ratio (ACLR) are also obtained by simulation. Results showed good agreement with the analytical results despite the use of the linear-approximation gain plus noise model. The EPWM transmitter that employed the first-order Δ-∑ modulator with a 0.1% clipping probability, an oversampling ratio of 32 and a three-pole Butterworth bandpass filter yielded an EVM of 1.8% and an ACLR of -37.9 dB, which are sufficiently lower than the OFDM transmitter specification.
8 citations
22 Jun 2014
TL;DR: A 4th-order DDSR with multi-bit quantizers and reconfigurable sampling frequency is adopted in the design and a maximum gain-control range of 18 dB is employed to respect the dynamic range specifications of the targeted standards.
Abstract: Direct Delta-Sigma Receiver (DDSR) architecture has emerged as an attractive solution for flexible receivers. In this paper, a reconfigurable DDSR architecture for GSM/WCDMA/LTE standards is presented. A 4th-order DDSR with multi-bit quantizers and reconfigurable sampling frequency is adopted in the design. A maximum gain-control range of 18 dB is employed to respect the dynamic range specifications of the targeted standards. A noise figure of 2.5 dB and a −5 dBm out-of-band IIP3 (OOB-IIP3) are achieved in this design.
8 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...This task is mainly done by using DS-Toolbox from Mathworks [9]....
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...Based on the above assumptions, the well-known calculations and curves proposed in [9] and the implementation constraints, the oversampling ratios (OSR), the sampling frequencies, and the NOB for all targeted standards are found....
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19 May 2013
TL;DR: Mixed-signal feedback utilizing the properties of a ΣΔ ADC is proposed to achieve a low cut-off frequency with 60 dB linearity and is designed to be implemented in 0.18 μm CMOS AMS technology.
Abstract: Integrating time constants of the order of a few seconds is one of the main bottlenecks in the design of biomedical chips. To achieve a low cut-off frequency with 60 dB linearity, mixed-signal feedback utilizing the properties of a ΣΔ ADC is proposed. To verify the performance, a 10-bit ΣΔ modulator with the proposed technique is designed to be implemented in 0.18 μm CMOS AMS technology. The design is verified by means of simulations in Cadence using RF spectre.
8 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...A continuous-time Σ∆ modulator has been used to reduce power consumption since a sample-and-hold stage is not needed [10]....
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...Choosing a resolution of 12 bits, to meet 10 bits overall resolution, an oversampling ratio of 512 would be required for a 1 order modulator [10], or in other words a sampling frequency of 256 kHz....
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01 Aug 2007
TL;DR: In this article, the authors proposed a feed-forward architecture of a second-order DeltaSigmaAD modulator with single DAC- feedback topology, which realized the summation of feedforward signals without additional amplifier that is equivalent to the conventional one but smaller chip area and low power dissipation.
Abstract: This paper proposes novel feedforward architecture of a second-order DeltaSigmaAD modulator with single DAC- feedback topology. DeltaSigmaAD modulator realizes high resolution by oversampling and noise shaping technique. However, its SNDR (signal to noise and distortion ratio) is limited by the dynamic range of the input signal and non-idealities of building blocks, particularly by the harmonic distortion in amplifier circuits. Compared with a feed backed DeltaSigmaAD modulator, in a full feedforward DeltaSigmaAD modulator structure, the signal transfer function is unity under ideal circumstances. It means that the signal swings through the loop filter become smaller. Therefore, the harmonic distortion generated inside the loop filter can be significantly reduced because the effect of non-idealities in amplifiers can be suppressed when signal swing is small. Moreover, the reduction of the internal signal swings also relaxes output swing requirement for amplifiers in low-voltage design. However, in conventional feedforward DeltaSigmaAD modulator, an analog adder is needed before quantizer. Especially in a multibit modulator, an additional amplifier is necessary to realize the summation of feedforward signals, which leads to large chip area and extra power dissipation. In this paper, we propose a novel architecture of a feedforward DeltaSigmaAD modulator. It realizes the summation of feedforward signals without additional amplifier that is equivalent to the conventional one but smaller chip area and low-power dissipation. We also conducted MATLAB and SPICE simulations to verify the proposed architecture and modulator circuits.
8 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...Therefore, the modulator becomes more linear, stability is improved and power dissipation is lower also [6]....
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References
More filters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations