Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
More filters
18 Dec 2014
TL;DR: The proposed system overcomes the inherent signal quality limits of digital systems with fixed clock frequencies by applying a phase modulated clock and demonstrates that it is possible to achieve the performance of conventional concepts at less than half of the bit rate.
Abstract: This paper describes a novel concept to encode amplitude and phase information in binary waveforms for switch-mode power amplifiers (SMPAs). A combination of a phase-modulated delta-sigma modulation (DSM) and pulse-width modulation (PWM) makes it possible to adapt signal generation to the power amplifier limits. The proposed system overcomes the inherent signal quality limits of digital systems with fixed clock frequencies by applying a phase modulated clock. We demonstrate that it is possible to achieve the performance of conventional concepts at less than half of the bit rate. Simulation and measurement results are given for important figures of merit of mobile communication signals with high peak-to-average power ratio (PAPR). A proof of concept is implemented in a laboratory setting using a conventional FPGA.
8 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...They can improve ACLR significantly [2], but this is beyond the scope of this paper....
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...A good overview of the basic concepts and variations of delta-sigma modulation (DSM) is given in [2]....
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31 Aug 2010
TL;DR: The design and FPGA implementation of a 2nd order all-digital Adaptive Delta Sigma (¿∑) modulator with one bit quantization, which exhibits an average SQNR improvement and an increase in the overall Signal to Quantization Noise Ratio (SQNR) of the modulator.
Abstract: This paper presents the design and FPGA implementation of a 2nd order all-digital Adaptive Delta Sigma (?∑) modulator with one bit quantization. It has a modulator stage and an adaptation stage. The adaptation stage produces a feedback signal that tracks the input signal and is subtracted from it. This difference signal is in a controlled and reduced range. It is given to the input of the modulator stage which has a 2nd order ?∑ modulator. This results in a reduction of quantization noise and an increase in the overall Signal to Quantization Noise Ratio (SQNR) of the modulator. The design was implemented on a Xilinx Spartan family FPGA using the Xilinx System Generator for DSP tool. The Hardware Co-Simulation mode of the System Generator was used which enables Simulink to run the FPGA directly, thus facilitating extensive testing. The spectral and SQNR analysis of the FPGA output was performed in MATLAB. The 2nd order adaptive ?∑ modulator presented here, exhibits an average SQNR improvement of 24.66 dB, 22.11 dB, 16.59 dB and 8.24 dB over the 2nd order non-adaptive ?∑ modulator at Over Sampling Ratios (OSRs) of 512, 256, 128 and 64 respectively in an input power range of -80 to 20 dB. It also exhibits an increased dynamic range of approximately 24 dB over the 2nd order non-adaptive ?∑ modulator.
8 citations
Proceedings Article•
11 Dec 2013TL;DR: The present paper proposes an alternate approach of controller implementation based on single-bit signal processing, which requires less interface channels between the controller and other parts of the system and thereby consumes significantly less hardware resources compared to traditional multi-bit processing.
Abstract: The traditional approach of controller implementation is based on multi-bit signal processing. The present paper proposes an alternate approach of controller implementation based on single-bit signal processing. This requires less interface channels between the controller and other parts of the system and thereby consumes significantly less hardware resources compared to traditional multi-bit processing. The effectiveness of the proposed single-bit or bit-stream controller is experimentally illustrated by designing two single-bit PID controllers for controlling the position of a D.C. Motor. The outer loop PID controller is designed to provide appropriate reference for the inner speed control loop, which is controlled by an inner loop PID controller. Various functional blocks are designed to implement Proportional, Integral and Derivative action in single-bit environment. Experimental results from a laboratory prototype illustrate that the single-bit based PID controllers effectively controls the position and consumes approximately 500 logic elements (LE) on an Altera Cyclone FPGA.
8 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...More details about the bit-stream and ΔΣ-modulator can be found in [7]....
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TL;DR: A phase-based delta–sigma (ΔΣ) analog-to-digital converter (ADC) is proposed and the idea is demonstrated using two architectures, which offers both reference jitter shaping and quantization noise shaping.
Abstract: A phase-based delta–sigma (ΔΣ) analog-to-digital converter (ADC) is proposed and the idea is demonstrated using two architectures. The first architecture adopts a delay-locked-loop (DLL) mechanism. It is realized by a modification of a DLL using a voltage-controlled delay line (VCDL) based quantizer and a charge pump in the feedback path. The proposed architecture offers both reference jitter shaping and quantization noise shaping. Simulation results show that the proposed ΔΣ ADC achieved 50.5 dB SNDR or 8.09 bits resolution for a 10 MHz signal bandwidth. The second architecture adopts a combination of voltage-controlled and digitally-controlled delay lines (VCDL–DCDL) as the phase-domain counterparts of an ADC–DAC in a traditional delta–sigma modulator. Simulation results of the new modulator achieve a 57.8 dB SNR, or a 9.28 bit over a 10 MHz bandwidth.
8 citations
23 Sep 2011
TL;DR: In this paper, a method to compensate the excess loop delay (ELD) in CT ΣΔ modulators using Gm-C loop filter is presented, which uses a resistor in series with the integration capacitor to obtain a feed-forward adder in the GmC integrator.
Abstract: A method to compensate the Excess Loop Delay (ELD) in CT ΣΔ modulators using Gm-C loop filter is presented. The proposed circuit architecture uses a resistor in series with the integration capacitor to obtain a feed-forward adder in the Gm-C integrator. The proposed ELD compensation is based on the Proportional Integrating (PI) - element method for low power dissipation and simple implementation, and it is verified through the design of a 2nd order CT ΣΔ modulator which uses a Gm-C integrator as the 2nd stage of the loop filter. To further demonstrate the efficiency of the technique a Non-Return-to-Zero (NRZ) feedback is utilized due to its larger sensitivity to ELD. Simulation results show that a 68.9dB SNDR can be achieved with an ELD close to half clock period, while the system will be unstable without compensation for such an amount of the loop delay. These results confirm the effectiveness of the proposed ELD compensation method in Gm-C filter based CT ΣΔ modulators.
8 citations
References
More filters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations