Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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Proceedings Article•
01 Jan 2011TL;DR: A two-stage pipeline ADC architecture with a large first-stage resolution, enabled with the help of a SAR-based sub-ADC, achieves low-power, high-resolution and high-speed operation without calibration.
Abstract: Successive approximation register (SAR) ADC architectures are popular for achieving high energy efficiency but they suffer from resolution and speed limitations. On the other hand pipeline ADC architectures can achieve high resolution and speed but have lower energy-efficiency and are more complex. We propose a two-stage pipeline ADC architecture with a large first-stage resolution, enabled with the help of a SAR-based sub-ADC. The prototype 12b 50 MS/s ADC achieves an ENOB of 10.4b at Nyquist, and a figure-of-merit of 52 fJ/conversion-step. The ADC achieves low-power, high-resolution and high-speed operation without calibration. The ADC is fabricated in 65 nm and 90 nm CMOS and occupies a core area of only 0.16 mm 2 .
8 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...Most of the architecture details of this stage are explained in Sections III-A and III-B....
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06 Nov 2014
TL;DR: This paper presents a digitally calibrated 12bit 12.5-MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) intended for low-power wireless communication and medical instrumentation and a power saving strategy is proposed.
Abstract: This paper presents a digitally calibrated 12bit 12.5-MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) intended for low-power wireless communication and medical instrumentation. The performance of the proposed prototype is enhanced by two techniques. A power saving strategy is proposed. Also, several foreground calibration methods for SAR ADCs are proposed to reduce the power dissipation and enhance the conversion accuracy. The design was fabricated in the GlobalFoundries 40 nm CMOS technology. Measurement results showed that after calibration a SFDR of 87.5 dB and a THD improvement of 24.3 dB were achieved.
8 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...For example, the bias currents of the preamplifiers, if any, and/or the comparator can be dynamically adjusted, based on the comparison's timing information....
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20 May 2012
TL;DR: The simulation results of a 10-bit SAR ADC with the proposed calibration methods show almost 10 effective number of bits (ENOB) with up to 0.5 % binary-weighted DAC mismatch, and more than 12 dB SNDR improvement for even larger DAC mismatch compared to that without calibration.
Abstract: New foreground digital calibration methods are proposed for successive approximation register (SAR) analog-to-digital converters (ADCs) to reduce the performance loss due to digital-to-analog converter (DAC) mismatch. A set of calibration coefficients which represent the actual weights of the specified patterns is obtained during foreground calibration, and then used during normal operation to correct the SAR ADC output using only a few multiplexers and an accumulator. The simulation results of a 10-bit SAR ADC with the proposed calibration methods show almost 10 effective number of bits (ENOB) with up to 0.5 % binary-weighted DAC mismatch, and more than 12 dB SNDR improvement for even larger DAC mismatch, compared to that without calibration.
8 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...To reduce capacitor mismatch, the DAC capacitor size is usually much larger than that needed by sampling noise consideration [3]....
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TL;DR: A slewing mitigation technique is presented where just the right amount of charge is provided at the switching instant to the SC circuit so that OTA does not need to provide high peak current, and may eliminate slewing altogether.
Abstract: Slewing in switched capacitor (SC) circuits reduces the available time for linear settling, and hence increases the nonlinear settling error. This transient demand in current can be supplied by making the bias currents larger in the operational transconductance amplifier (OTA). However, this increases the static power consumption significantly. In this paper a slewing mitigation technique is presented where just the right amount of charge is provided at the switching instant to the SC circuit so that OTA does not need to provide high peak current. This may eliminate slewing altogether, and allows using OTAs with less static current for the same settling accuracy. The operation of the proposed technique is illustrated by incorporating it in a second-order delta-sigma modulator (DSM). The modulator was designed and simulated in a 65nm CMOS process. Post-layout extracted simulations with optimized design show more than 12 dB improvement in signal to noise and distortion ratio (SNDR) for the same static power. Alternatively, compared to a DSM without such technique, the same performance can be achieved with 30% less power.
8 citations
Cites methods from "Understanding Delta-Sigma Data Conv..."
...A single-bit second order DSM low distortion structure [22] was chosen as a test case for circuit implementation as shown in Fig....
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...Low distortion second-order DSM architecture [22]....
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TL;DR: In this article, a low voltage continuous-time delta-sigma modulator (DSM) is proposed for the receiver of an ultra-low-power radio, which uses a 2nd-order loop filter implemented with a single operational amplifier to reduce the power consumption.
Abstract: This paper presents a low voltage continuous-time delta---sigma modulator (DSM) intended for the receiver of an ultra-low-power radio. The DSM features a 2nd-order loop filter implemented with a single operational amplifier to reduce the power consumption. Furthermore, a 4-bit quantizer is used to achieve high resolution while keeping the sampling frequency low. The quantizer is realized using the successive approximation register architecture with asynchronous control which is more power efficient than the commonly used flash architecture. The DSM has been implemented in a 65 nm CMOS process. Simulation results show a peak SNDR of 65 dB over a 500 kHz signal bandwidth. The DSM consumes 69 $${\upmu }$$μW from a 800 mV power supply.
8 citations
References
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TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations