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Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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TL;DR: A high-resolution time-to-digital converter (TDC) using switched-ring oscillators (SROs) is presented, capable of operating at high oversampling ratios (OSRs) and achieving high resolution without the need for calibration.
Abstract: A high-resolution time-to-digital converter (TDC) using switched-ring oscillators (SROs) is presented. Leveraging oversampling and noise shaping, the proposed SRO-TDC achieves high resolution without the need for calibration. Ring oscillators are switched between two frequencies to achieve noise shaping of the quantization error in an open-loop manner. By decoupling the sampling clock and input carrier frequencies, SRO-TDC is capable of operating at high oversampling ratios (OSRs). This paper also discusses different noise sources and quantization/device noise tradeoffs in noise-shaping TDCs and presents techniques to characterize TDC linearity, range, and noise performance. Fabricated in 90 nm CMOS technology, the proposed TDC operates over a wide range of input carrier frequencies (0.6-750 MHz) and sampling rates (50-750 MS/s). At 500 MS/s and 80 MHz carrier frequency, it achieves an integrated noise of 315 fs in a 1 MHz bandwidth while consuming 1.5 mW from a 1 V supply. The SRO-TDC occupies an active die area of only 0.02 mm2.
71 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...Bymodeling this process as passing the quantization error through the so called noise transfer function, which equals to , the output noise power spectral density is obtained as [15]...
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...Assuming to be much greater than , the variance of the quantization noise can be approximated to [15]...
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TL;DR: This paper presents a second-order NS-SAR ADC employing the error-feedback (EF) structure to realize complex NTF zeros for noise-shaping enhancement with the minimum modification to a standard SAR.
Abstract: The noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) is an emerging hybrid architecture that achieves high resolution and power efficiency simultaneously by combining the merits of the SAR ADC and the $\Delta \Sigma $ ADC. Most prior works adopting the cascaded integrator feed-forward (CIFF) structure demonstrate inefficiency in realizing optimized noise transfer function (NTF). This paper presents a second-order NS-SAR ADC employing the error-feedback (EF) structure to realize complex NTF zeros for noise-shaping enhancement with the minimum modification to a standard SAR. It implements a low-power scaling-friendly EF path by using a passive finite impulse response (FIR) and a comparator-reused dynamic amplifier with process-voltage-temperature (PVT) tracking background calibration. Fabricated in 40-nm CMOS, the prototype chip consumes $84~\mu \text{W}$ when operating at 10 MS/s. The NS-SAR achieves peak Schreier FoM of 178 dB with 79-dB signal to noise and distortion ratio (SNDR) at an oversampling ratio (OSR) of 8.
71 citations
Cites methods from "Understanding Delta-Sigma Data Conv..."
...Following the analysis in [23], for a second-order system, the optimum frequency of the zeros that Fig....
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...Owing to this drawback, the EF structure used to only function as an order booster at the backend of a high-order integrator-based loop where its non-idealities causes little impact [23], [24], thereby much restricting its potential....
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TL;DR: This ECG sensor node can accurately record and detect the QRS peaks of ECG waveform with high-frequency noise suppression and is convenient for long-term monitoring of cardiovascular condition of patients, and is very suitable for on-body WBAN applications.
Abstract: This paper proposes a power and area efficient electrocardiogram (ECG) acquisition and signal processing application sensor node for wireless body area networks (WBAN). This sensor node can accurately record and detect the QRS peaks of ECG waveform with high-frequency noise suppression. The proposed system is implemented in 0.18-μm complementary metal-oxide-semiconductor technology with two chips: analog front end integrated circuit (IC) and digital application specific integrated circuit (ASIC), where the analog IC consumes only 79.6 μW with area of 4.25 mm2 and digital ASIC consumes 9 μW at 32 kHz with 1.2 mm2. Therefore, this ECG sensor node is convenient for long-term monitoring of cardiovascular condition of patients, and is very suitable for on-body WBAN applications.
70 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...Single-loop 1-bit sigma-delta ADC was particularly selected due to its simplicity and insensitivity to imperfections of analog circuits [24], [25]....
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TL;DR: This paper provides a comprehensive review of EM-ΣAM interfaces for capacitive MEMS inertial sensors and the properties of various discrete and continuous-time techniques and a system parameter optimization methodology are illustrated through specific examples.
Abstract: Analog-to-digital converters based on sigma–delta modulators ( $\Sigma \Delta {\mathrm{ M}}$ ) are a popular choice for high resolution conversion from the analog to the digital domain. With relatively small modifications, they can also be used as electromechanical $\Sigma \Delta {\mathrm{ M}}$ (EM- $\Sigma \Delta {\mathrm{ M}}$ ) force feedback interfaces for capacitive micro-electromechanical systems (MEMSs) inertial sensors. Such interfaces are able to combine the benefits of force feedback and analog-to-digital conversion at relatively modest circuit cost. This paper provides a comprehensive review of EM- $\Sigma \Delta {\mathrm{ M}}$ interfaces for capacitive MEMS inertial sensors. The principle and the design methodology of EM- $\Sigma \Delta {\mathrm{ M}}$ interfaces are introduced. A classification of EM- $\Sigma \Delta {\mathrm{ M}}$ accelerometers and gyroscopes is presented, and a detailed analysis of different EM- $\Sigma \Delta {\mathrm{ M}}$ architectures is given. The most representative EM- $\Sigma \Delta {\mathrm{ M}}$ inertial sensors systems are discussed and compared with regard to their performance characteristics. In particular, the properties of various discrete and continuous-time techniques and a system parameter optimization methodology are illustrated through specific examples. Finally, current challenges and future development trends of EM- $\Sigma \Delta {\mathrm{ M}}$ interfaces for inertial sensors have been identified.
68 citations
Cites methods from "Understanding Delta-Sigma Data Conv..."
...An approach described to find the optimal linear system parameters was based on a root locus approach [36] and a stability criteria for the noise transfer function (NTF gain < 1....
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TL;DR: This paper presents the first dynamic zoom ADC, intended for audio applications, which achieves 109-dB DR, 106-dB signal-to-noise ratio, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating only 1.12 mW.
Abstract: This paper presents the first dynamic zoom ADC. Intended for audio applications, it achieves 109-dB DR, 106-dB signal-to-noise ratio, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating only 1.12 mW. This translates into the state-of-the-art energy efficiency as expressed by a Schreier FoM of 181.5 dB. It also achieves the state-of-the-art area efficiency, occupying only 0.16 mm2 in the 0.16- $\mu \text{m}$ CMOS. These advances are enabled by the use of concurrent fine and coarse conversions, dynamic error-correction techniques, and a dynamically biased inverter-based operational transconductance amplifier.
68 citations
References
More filters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations