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Understanding Delta-Sigma Data Converters
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TLDR
This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.Abstract:
Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.read more
Citations
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Journal ArticleDOI
A Sub-Picosecond Resolution 0.5–1.5 GHz Digital-to-Phase Converter
TL;DR: A new DPC architecture is presented that achieves high resolution independent of both the operating frequency and the rise time of the interpolator inputs, and is fabricated in a 0.13 mum CMOS process.
Journal ArticleDOI
Next-Generation Delta-Sigma Converters: Trends and Perspectives
TL;DR: This paper presents an overview of emerging circuits and systems techniques which are at the forefront of the state of the art in ΔΣ modulators, pushing their performance forward and giving rise to new generations of data converters.
Journal ArticleDOI
A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance
TL;DR: This paper presents a reference-less half-rate CDR that uses a sub-harmonic extraction method to achieve unlimited frequency acquisition range, and is capable of locking the CDR to within 40ppm of any sub-rate of the data, while being immune to undesirable harmonic locking.
Journal ArticleDOI
Sturdy MASH /spl Delta//spl Sigma/ modulator
TL;DR: Simulation results and mathematical analysis demonstrate the effectiveness of a new Delta-Sigma modulator that is similar to that of a multi-stage noise-shaping structure but requires no digital noise cancellation filters.
Journal ArticleDOI
A Micro-Power Two-Step Incremental Analog-to-Digital Converter
TL;DR: The measured results verify that the proposed two-step IADC is a more energy-efficient data conversion scheme than conventional high-order IADCs.
References
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Journal ArticleDOI
A higher order topology for interpolative modulators for oversampling A/D converters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Journal ArticleDOI
Decimation for Sigma Delta Modulation
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Journal ArticleDOI
An analysis of nonlinear behavior in delta - sigma modulators
Sasan H. Ardalan,J.J. Paulos +1 more
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Book ChapterDOI
The Structure of Quantization Noise from Sigma-Delta Modulation
James C. Candy,O. Benjamin +1 more
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Journal ArticleDOI
A fourth-order bandpass sigma-delta modulator
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.