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Understanding Delta-Sigma Data Converters

TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

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Citations
More filters
Journal ArticleDOI
TL;DR: In this paper, a 2nd-order 4-bit continuous-time (CT) delta-sigma modulator (DSM) was proposed for ultra-low-power radios.
Abstract: We present a 2nd-order 4-bit continuous-time (CT) delta-sigma modulator (DSM) employing a 2nd-order loop filter with a single operational amplifier. This choice strongly reduces the power consumption, since operational amplifiers are the most power hungry blocks in the DSM. The DSM has been implemented in a 65 nm CMOS process, where it occupies an area of $$0.08\,\hbox {mm}^2$$ 0.08 mm 2 . It achieves an SNDR of 64 dB over a 500 kHz signal bandwidth with an oversampling ratio of 16. The power consumption is $$76\,\upmu \hbox {W}$$ 76 μ W from a 800 mV power supply. The DSM figure-of-merit is 59 fJ/conversion. The CT DSM is well suited for the receiver of an ultra-low-power radio.

6 citations

Proceedings ArticleDOI
04 May 2014
TL;DR: This paper addresses this opportunity by deriving the optimal DAC bit resolution vs frequency shape for maximizing the information content in the channel output given a power constraint.
Abstract: DACs are usually defined as having a constant number of bits over a contiguous bandwidth. Signals in practice, however, frequently have an information or bit content which is not constant with frequency. As DAC power is a function of bits, this creates an opportunity to design a more power efficient DAC. This paper addresses this opportunity by deriving the optimal DAC bit resolution vs frequency shape for maximizing the information content in the channel output given a power constraint. An optimization method that works within the constraints of the delta sigma modulator is also developed as arbitrary noise shaping is not possible with a fixed delta sigma DAC architecture.

6 citations


Cites background or methods from "Understanding Delta-Sigma Data Conv..."

  • ...Index Terms— DACs, information, noise shaping, delta sigma...

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  • ...On the theory side, this paper extends these ideas to DACs....

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  • ...The conventional design with zeros optimized to minimize the in band DAC noise [5] was compared to the proposed design with zeroes optimized based on maximizing information....

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  • ...For practical noise shaping in delta sigma DACs, [4] and [5] optimized the zeros of the NTF to minimize the total integrated noise power....

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  • ...DACs are usually defined as having a constant number of bits over a contiguous bandwidth and consume power which is approximately proportional to 2bits x bandwidth....

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Journal ArticleDOI
TL;DR: Experimental results show that this digital decimation filter is suitable for use in oversampled data converters and can be applied to new processes requiring a fast redesign time because it does not have process-dependent ROM or RAM circuits.
Abstract: Digital decimation filters are used in delta-sigma analogue-to-digital converters to reduce the oversampled data rate to the final Nyquist rate. This paper presents the design and implementation of a fully synthesised digital decimation filter that provides a time-to-market advantage. The filter consists of a cascaded integrator-comb filter and two cascaded half-band FIR filters. A canonical signed-digit representation of the filter coefficients is used to minimise the area and to reduce the hardware complexity of the multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated by using 0.25-μm CMOS technology with an active area of 1.36 mm2 and shows 4.4 mW power consumption at a clock rate of 2.8224 MHz. Experimental results show that this digital decimation filter is suitable for use in oversampled data converters and can be applied to new processes requiring a fast redesign time. This is possible because the filte...

6 citations


Cites background or methods from "Understanding Delta-Sigma Data Conv..."

  • ...As the CIC filter has a passband droop, a relatively simple extra stage might be required as a droop-compensation filter (Schreier and Temes 2005)....

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  • ...Oversampled delta-sigma analogue-to-digital converters (ADCs) have been widely used in high-resolution data converters (Schreier and Temes 2005; Roh et al. 2008, 2009)....

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Journal ArticleDOI
TL;DR: In this paper, a voltage-controlled oscillator (VCO)-based 1-1 MASH delta-sigma ADC structure is presented, which does not require any operational transconductance amplifier-based analog integrators or integrating capacitors.
Abstract: In this paper, a new voltage-controlled oscillator (VCO)-based 1-1 MASH delta–sigma ADC structure is presented. The proposed architecture does not require any operational transconductance amplifier-based analog integrators or integrating capacitors. Second-order noise shaping is achieved by using a VCO as an integrator in the feedback loop of the first stage and an open-loop VCO quantizer in the second stage. Simple digital circuitry extracts the phase quantization error of the first stage as a pulse signal that is applied to the second stage. The input of the first VCO is a very small amplitude signal, and the input of the second VCO is a two-level PWM signal. Therefore, the VCO non-linearity does not limit the overall ADC performance, mitigating the need for the power hungry linearization methods. The proposed idea was simulated at the transistor level, and the results verify the analysis.

6 citations

Journal ArticleDOI
TL;DR: In this paper, the impact of random and deterministic output pulse position jitter (PPJ) on a superconducting voltage reference waveform synthesizer with fundamentally accurate output pulses is quantified.
Abstract: We present the first jitter sensitivity analysis of a superconducting voltage reference waveform synthesizer with fundamentally accurate output pulses. Successful deployment of a reference waveform source at microwave frequencies will represent a new paradigm for radio frequency metrology. The programmable waveform synthesizer considered in this paper contains a 1.5 bit delta–sigma digital-to-analog converter (DAC) with a sampling frequency of 28 GHz. We quantify the impact of random and deterministic output pulse position jitter (PPJ) on: 1) the amplitude accuracy of the output fundamental tone and 2) the in-band signal-to-noise and distortion ratio (SNDR). The superconducting DAC features a complete lack of output pulsewidth jitter, and random PPJ up to 200 fs rms has a negligible impact on accuracy and SNDR for synthesized tones up to 1 GHz. However, application of nonzero dc bias current is shown to produce deterministic PPJ of up to 5 ps, which, in turn, is shown to degrade the in-band SNDR by 30 dB at 1 GHz unless eliminated with techniques discussed in this paper. We verify the predicted effects of random and deterministic PPJ with simulations in the range of 100 kHz–1 GHz and with experiments in the range of 100 kHz–3 MHz.

6 citations


Cites background or methods from "Understanding Delta-Sigma Data Conv..."

  • ...We use a low-pass or bandpass delta–sigma encoding algorithm to move the quantization noise out of band [15]....

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  • ...frequencies that are typically out of band [14], [15]....

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  • ...This feature has a high-pass filtering effect on the power spectral density (PSD) of the error signal [15]....

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  • ...tectures report extensive efforts to minimize PWJ [16], [17], even at the expense of degraded linearity and increased circuit complexity [15], [18]....

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References
More filters
Journal ArticleDOI
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >

399 citations

Journal ArticleDOI
James C. Candy1
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.

342 citations

Journal ArticleDOI
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.

284 citations

Book ChapterDOI
James C. Candy1, O. Benjamin1
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.

255 citations

Journal ArticleDOI
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >

211 citations