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Understanding Delta-Sigma Data Converters

TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

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Citations
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Journal ArticleDOI
TL;DR: A 5th-Order single-loop low distortion Sigma–Delta Modulator (SDM) is implemented with the combination of the comparator-based switched-capacitor (CBSC)-based and op-amp-based techniques for asymmetric digital subscriber line (ADSL) applications.
Abstract: In this letter, a 5th-Order single-loop low distortion Sigma---Delta Modulator (SDM) is implemented with the combination of the comparator-based switched-capacitor (CBSC)-based and op-amp-based techniques for asymmetric digital subscriber line (ADSL) applications. This structure, which uses integrator (CBSC-based) and IIR filter (op-amp-based) concurrently, has relatively fewer feed-forward paths and modulator coefficients for sensitivity reduction to mismatch. To lower the power consumption of the modulator, the integrators are implemented with CBSC, the IIR filter block is implemented by single OTA, and a passive adder is used to realize the adder at the input of the 5-bit quantizer. The design purpose is minimizing the power consumption while the dynamic performance maintains high. As shown in the simulation result, for a 2-MHz signal bandwidth, the modulator achieves a dynamic range (DR) of 86.5 dB and a peak signal-to-noise and distortion ratio (SNDR) of 85 dB with an oversampling ratio of 8. In addition it consumes 18.75 mW from a 1.8-V power supply at 32 MS/s, which obtains a figure of merit of 1.6e?3.

6 citations


Cites background from "Understanding Delta-Sigma Data Conv..."

  • ...6e-4 Hz [17], the maximum values for the SNDR are 101 dB in the SIMULINK, 91....

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Journal ArticleDOI
TL;DR: In this article, a pulse-encoded transition (PET) technique is introduced to reduce undesired harmonic distortion (HD) and adjacent channel leakage ratio (ACLR) generated by the direct RF modulation.
Abstract: This article reports signal processing and circuit techniques for direct RF signal modulation. A pulse-encoded transition (PET) technique is introduced to reduce undesired harmonic distortion (HD) and adjacent channel leakage ratio (ACLR) generated by the direct RF modulation. To enable PET RF switching, two variations of a high-power, stacked-FET switch modulator, an 8- and 12-device stack, are designed in 45-nm silicon on insulator (SOI) CMOS. The switch design uses a tapering design to significantly improve power handling with minimal impact to switching speed. The modulators have $P_{1\,{\mathrm{ dB}}} $ values between 34 and 39 dBm while demonstrating a modulation bandwidth of nearly 500 MHz with a 1-GHz carrier. The input referred third order intercept point (IIP3) is between 46 and 61 dBm. Additionally, ACLR measurements of up to −50 dBc are demonstrated using the proposed PET technique at 30-dBm output power. To the best of our knowledge, this is record power handling and ACLR for a CMOS switch.

6 citations


Cites background from "Understanding Delta-Sigma Data Conv..."

  • ...9, the input power of the signal must be backed off ∼3 dB in order to increase the chance of stability [39]....

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Journal ArticleDOI
TL;DR: In this paper, a noise shaping technique was proposed to reshape the white quantization noise to an irregular spectrum, in which the noise in the data subcarrier band is almost transformed into the null subcrier band.
Abstract: In order to reduce the quantization noise of low-resolution DAC, we study a noise shaping technique that can reshape the white quantization noise to an irregular spectrum, in which the noise in the data subcarrier band is almost transformed into the null subcarrier band. Both in simulation and experiment, we verify the effectiveness of the investigated scheme in 25 GHz 16-QAM/32-QAM/64-QAM DMT transmission systems. The experimental results show that the noise shaping technique can enhance the receiver sensitivity of 4-bit quantized 16-QAM DMT and 5-bit quantized 32-QAM DMT by 4.3 dB and 2.5 dB respectively, at BER of hard decision forward error correction (HD-FEC) threshold (3.8 × 10−3). In addition, with the aid of noise shaping, the performance of 4-bit quantization 16-QAM DMT system is the same as the 8-bit quantization 16-QAM DMT system at the HD-FEC threshold. The experimental results reveal that the proposed noise shaping scheme is a good solution for high-speed, low-cost short reach intra-DCI with low-resolution DAC in future 6G networks evolved from 5G mobile networks.

6 citations

Journal ArticleDOI
TL;DR: This paper presents a 14.9-bit 3.57-MS/s algorithmic ADC that uses iterative gain enhancement, a technique that uses multiple clock phases to increase the effective op-amp gain in a switched-capacitor circuit.
Abstract: This paper presents a 14.9-bit 3.57-MS/s algorithmic ADC that uses iterative gain enhancement, a technique that uses multiple clock phases to increase the effective op-amp gain in a switched-capacitor circuit. Using an op-amp that gives only 30-dB loop gain in a feedback circuit without gain enhancement, application of the iterative gain enhancement technique boosts the loop gain to 81 dB. The algorithmic ADC uses a capacitor sharing and scaling technique, which saves power and reduces errors. The ADC has an active area of 0.75 $\text{mm}^{2}$ in 0.25- $\mu\text{m}$ CMOS and dissipates 16.2 mW. Iterative gain enhancement increases the SNDR from 44.6 dB to 78.5 dB and the SFDR from 45.9 dB to 96.2 dB. Reducing the number of gain-enhancement iterations for the LSBs increases the conversion rate from 3.57 MS/s to 4.65 MS/s with only minor performance degradation.

6 citations

Proceedings ArticleDOI
01 Aug 2007
TL;DR: A detailed derivation of the digital cancellation filters for continuous-time cascaded sigma-delta modulators is presented in order to achieve maximum signal- to-noise ratio together with optimal anti-aliasing performance.
Abstract: This paper deals with a systematic approach to the synthesis of continuous-time cascaded sigma-delta modulators. Based on a system-theoretical model, a detailed derivation of the digital cancellation filters for continuous-time cascaded architectures is presented in order to achieve maximum signal- to-noise ratio together with optimal anti-aliasing performance. By the same model, an exact equation for the performance loss of any cascaded architecture is derived. Finally, an analytical calculation of optimal scaling coefficients in between the stages is performed, resulting in a limited search-space for these coefficients. Theoretical results are verified by simulations.

6 citations

References
More filters
Journal ArticleDOI
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >

399 citations

Journal ArticleDOI
James C. Candy1
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.

342 citations

Journal ArticleDOI
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.

284 citations

Book ChapterDOI
James C. Candy1, O. Benjamin1
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.

255 citations

Journal ArticleDOI
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >

211 citations